HV4622PJ-G Supertex, HV4622PJ-G Datasheet

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HV4622PJ-G

Manufacturer Part Number
HV4622PJ-G
Description
Counter Shift Registers 220V 32C Opn D w/CCW
Manufacturer
Supertex
Datasheet

Specifications of HV4622PJ-G

Product Category
Counter Shift Registers
Rohs
yes
Counting Sequence
Serial to Serial/Parallel
Number Of Circuits
1
Package / Case
PLCC-44
Logic Type
CMOS
Number Of Input Lines
1
Output Type
Open Drain
Propagation Delay Time
100 ns
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Function
Shift Register/Latch/Driver
Mounting Style
SMD/SMT
Number Of Output Lines
33
Operating Supply Voltage
+ 0.5 V to - 16 V
Factory Pack Quantity
27
Supply Voltage - Max
13.2 V
Features
Functional Block Diagram
Processed with HVCMOS
Output voltages to -220V
Source current minimum 60mA
Shift register speed 8.0MHz
Polarity and blanking inputs
CMOS compatible inputs
Forward and reverse shifting options
Can be used with the HV5622 to provide 220V
push-pull operation
44-lead PLCC surface mount package
Supertex inc.
DATA INPUT
DATA OUT
POL
CLK
VSS
BL
LE
32-Channel Serial to Parallel Converter
with P-Channel Open Drain Outputs
®
Technology
Register
32-Bit
Shift
1235 Bordeaux Drive, Sunnyvale, CA 94089
Latch
Latch
Latch
Latch
General Description
The HV4622 is a low-voltage serial to high-voltage parallel
converter with P-Channel open drain outputs. This device has
been designed for use a driver for AC-electroluminescent
displays. It can also be used in any application requiring multiple
output high-voltage current source capabilities, such as driving
inkjet and electrostatic print heads, plasma panels, or vacuum
fluorescent displays.
This device consists of a 32-bit shift register, 32 data latches, and
control logic to perform polarity and blanking functions. Data is
shifted through the shift register on the logic high-to-low transition
of the clock. The HV4622 shifts in the clockwise direction (when
viewed from the top of the package). A data output buffer is
provided for cascading devices. This output reflects the current
status of the last bit of the shift register. The data in the shift
register is latched when the latch enable pin is brought to logic
high, and then returned to ground. If the latch enable pin is held
high, the latch becomes transparent and the shift register data is
directly reflected in the outputs.
For applications requiring active pull down as well as pull up, the
HV4622 can be paired with the HV5622.
Tel: 408-222-8888
www.supertex.com
(Outputs 3 to 30
not shown)
HV
HV
HV
HV
OUT
OUT
OUT
OUT
1
2
31
32
HV4622

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HV4622PJ-G Summary of contents

Page 1

... BL LE DATA INPUT CLK DATA OUT Supertex inc. General Description The HV4622 is a low-voltage serial to high-voltage parallel converter with P-Channel open drain outputs. This device has been designed for use a driver for AC-electroluminescent displays. It can also be used in any application requiring multiple ...

Page 2

... Low-level input voltage (Logic “0” Clock frequency CLK T Operating free-air temperature A Note: All voltages are referenced Supertex inc. .653x.653in body .050in pitch HV4622PJ-G Pin Configuration Value +0.5V to -16V +0.5V to -240V +0. -0.3V DD 1.5A 1200mW 2 -40°C to +85°C -65°C to +150°C Product Marking . ...

Page 3

... DLH t Delay time clock to LE high to low DLE t LE pulse width WLE t LE set-up time before clock rises SLE Input and Output Equivalent Circuits VSS INPUT VDD Logic Inputs Supertex inc. (Over recommended operating conditions unless otherwise noted) Min - - - - - V +1. OUT D ...

Page 4

... Transparent latch mode H ↓ Notes high level = -12V low level = 0V irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transition dependent on previous stage’s state before the last CLK high-to-low transition or last LE high. Supertex inc. Data Valid 50 ...

Page 5

... HV 19 OUT OUT OUT Supertex inc. Description High voltage outputs. No connect. Data output pin. No connect. Inverts the polarity of the HV OUT Clock pin, shift registers shifts data on rising edge of input clock. Reference voltage, usually ground. Logic supply voltage. Logic enable pin, data is shifted from shift register to latches on logic input low. ...

Page 6

... JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-44PLCCPJ, Version F031111. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives Supertex inc ...

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