74HC165D-Q100 NXP Semiconductors, 74HC165D-Q100 Datasheet - Page 4
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74HC165D-Q100
Manufacturer Part Number
74HC165D-Q100
Description
Counter Shift Registers 8 Bit Par-Ser Out 6V
Manufacturer
NXP Semiconductors
Datasheet
1.74HC165D-Q100.pdf
(21 pages)
Specifications of 74HC165D-Q100
Package / Case
SO-16
Logic Family
74HC
Logic Type
Shift Register
Output Type
Parallel / Serial
Propagation Delay Time
250 ns
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Function
8 Bit Parallel In Serial Out
Mounting Style
SMD/SMT
Operating Supply Voltage
2 V to 6 V
Product
Driver ICs - Various
Supply Voltage - Max
6 V
Supply Voltage - Min
2 V
Part # Aliases
74HC165D-Q100,118
NXP Semiconductors
Table 2.
7. Functional description
Table 3.
[1]
74HC_HCT165_Q100
Product data sheet
Symbol
PL
CP
Q7
GND
Q7
DS
D0 to D7
CE
V
Operating modes
parallel load
serial shift
hold “do nothing”
CC
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Pin description
Function table
Pin
1
2
7
8
9
10
11, 12, 13, 14, 3, 4, 5, 6
15
16
6.2 Pin description
Inputs
PL
L
L
H
H
H
H
H
H
[1]
CE
X
X
L
L
H
X
All information provided in this document is subject to legal disclaimers.
CP
X
X
L
L
X
H
Description
asynchronous parallel load input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
complementary output from the last stage
ground (0 V)
serial output from the last stage
serial data input
parallel data inputs (also referred to as Dn)
clock enable input (active LOW)
positive supply voltage
74HC165-Q100; 74HCT165-Q100
Rev. 1 — 17 July 2012
X
DS
X
X
l
h
l
h
X
D0 to D7 Q0
L
H
X
X
X
X
X
X
8-bit parallel-in/serial out shift register
Qn registers
L
H
L
H
L
H
q0
q0
Q1 to Q6 Q7
L to L
H to H
q0 to q5
q0 to q5
q0 to q5
q0 to q5
q1 to q6
q1 to q6
Outputs
H
q6
q6
q6
q6
q7
q7
L
© NXP B.V. 2012. All rights reserved.
Q7
H
L
q6
q6
q6
q6
q7
q7
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