74HC132D-Q100 NXP Semiconductors, 74HC132D-Q100 Datasheet - Page 13
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74HC132D-Q100
Manufacturer Part Number
74HC132D-Q100
Description
Logic Gates 2-IN NAND Gate 6V
Manufacturer
NXP Semiconductors
Datasheet
1.74HC132D-Q100.pdf
(18 pages)
Specifications of 74HC132D-Q100
Product
NAND
Logic Family
74HC
Number Of Gates
4
Number Of Lines (input / Output)
2 /
Propagation Delay Time
190 ns
Supply Voltage - Max
6 V
Supply Voltage - Min
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SO-14
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Operating Temperature Range
- 40 C to + 125 C
Output Current
25 mA
Power Dissipation
500 mW
Part # Aliases
74HC132D-Q100,118
NXP Semiconductors
16. Package outline
Fig 15. Package outline SOT108-1 (SO14)
74HC_HCT132_Q100
Product data sheet
SO14: plastic small outline package; 14 leads; body width 3.9 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
inches
UNIT
mm
VERSION
OUTLINE
SOT108-1
0.069
max.
1.75
A
0.010
0.004
0.25
0.10
A
14
1
1
Z
pin 1 index
y
0.057
0.049
1.45
1.25
A
2
076E06
IEC
0.25
0.01
e
A
3
0.019
0.014
0.49
0.36
b
p
D
0.0100
0.0075
All information provided in this document is subject to legal disclaimers.
0.25
0.19
MS-012
JEDEC
c
74HC132-Q100; 74HCT132-Q100
REFERENCES
8.75
8.55
0.35
0.34
D
(1)
Rev. 2 — 13 August 2012
0
0.16
0.15
E
4.0
3.8
b
(1)
p
8
7
JEITA
scale
1.27
0.05
2.5
e
w
M
c
0.244
0.228
H
6.2
5.8
E
A
2
0.041
5 mm
1.05
A
L
1
0.039
0.016
1.0
0.4
L
p
Quad 2-input NAND Schmitt trigger
H
E
E
detail X
0.028
0.024
0.7
0.6
Q
PROJECTION
L
L
EUROPEAN
0.25
0.01
p
Q
v
(A )
3
A
0.25
0.01
w
θ
0.004
A
0.1
© NXP B.V. 2012. All rights reserved.
X
v
y
M
ISSUE DATE
99-12-27
03-02-19
A
0.028
0.012
Z
0.7
0.3
(1)
SOT108-1
θ
8
0
13 of 18
o
o