HEF4093BT-Q100 NXP Semiconductors, HEF4093BT-Q100 Datasheet - Page 5

• Manufacturer Part Number: HEF4093BT-Q100
• Description: Logic Gates 2-IN NAND Gate 15V
• Manufacturer: NXP Semiconductors

Specifications of HEF4093BT-Q100

• Product: NAND
• Number Of Gates: 4
• Number Of Lines (input / Output): 2 /
• High Level Output Current: - 2.4 mA
• Low Level Output Current: 2.4 mA
• Supply Voltage - Max: 15 V
• Supply Voltage - Min: 3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SO-14
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Number Of Input Lines: 2
• Operating Temperature Range: - 40 C to + 125 C
• Output Current: 10 mA
• Power Dissipation: 500 mW
• Part # Aliases: HEF4093BT-Q100,118

NXP Semiconductors
11. Dynamic characteristics
Table 7.
T
[1]
Table 8.
V
HEF4093B_Q100
Product data sheet
Symbol Parameter
t
t
t
t
Symbol Parameter
P
PHL
PLH
THL
TLH
amb
SS
D
= 0 V; t
Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (C
= 25

HIGH to LOW
propagation delay
LOW to HIGH
propagation delay
HIGH to LOW output
transition time
LOW to HIGH output
transition time
dynamic power
dissipation
C; C
r
Dynamic characteristics
Dynamic power dissipation
= t
f
L

= 50 pF; t
20 ns; T
amb
r
= t
= 25
f

20 ns; wave forms see
V
10 V
15 V
5 V
DD

Conditions
nA or nB to nY
nA or nB to nY
nY to LOW
nA or nB to
HIGH
C.
Typical formula
P
P
P
All information provided in this document is subject to legal disclaimers.
D
D
D
= 1300  f
= 6400  f
= 18700  f
Rev. 1 — 12 July 2012
V
10 V
15 V
10 V
15 V
10 V
15 V
10 V
15 V
5 V
5 V
5 V
5 V
DD
i
i
+ (f
+ (f
i
Figure
+ (f
o
o
o
 C
 C
 C
4; test circuit see
Extrapolation formula
63 ns + (0.55 ns/pF)C
29 ns + (0.23 ns/pF)C
22 ns + (0.16 ns/pF)C
58 ns + (0.55 ns/pF)C
29 ns + (0.23 ns/pF)C
22 ns + (0.16 ns/pF)C
10 ns + (1.00 ns/pF)C
10 ns + (1.00 ns/pF)C
9 ns + (0.42 ns/pF)C
6 ns + (0.28 ns/pF)C
9 ns + (0.42 ns/pF)C
6 ns + (0.28 ns/pF)C
L
L
)  V
)  V
L
)  V
DD
DD
DD
2
2
2
(W)
(W)
(W)
Figure
Quad 2-input NAND Schmitt trigger
HEF4093B-Q100
where:
f
f
C
(f
V
L
L
L
L
L
L
L
L
L
L
L
L
i
o
DD
= input frequency in MHz;
L
[1]
= output frequency in MHz;
o
5; unless otherwise specified.
= output load capacitance in pF;
 C
= supply voltage in V.
Min
-
-
-
-
-
-
-
-
-
-
-
-
L
) = sum of the outputs;
Typ
90
40
30
85
40
30
60
30
20
60
30
20
© NXP B.V. 2012. All rights reserved.
L
in pF).
Max
185
170
120
120
80
60
80
60
60
40
60
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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