RSENC-DBLK-P2-U4 Lattice, RSENC-DBLK-P2-U4 Datasheet - Page 25

• Manufacturer Part Number: RSENC-DBLK-P2-U4
• Description: Encoders, Decoders, Multiplexers & Demultiplexers Dynamic Block Reed Solomon Encoder
• Manufacturer: Lattice

Specifications of RSENC-DBLK-P2-U4

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG40_03.6, August 2010
Instantiating the Core
The \<rsenc_eval> and subtending directories provide files supporting Dynamic Block Reed-Solomon Encoder
IP core evaluation. The \<rsenc_eval> directory shown in
is constant for all con-figurations of the Dynamic Block Reed-Solomon Encoder. The \<username> subfolder
(\resnc_core0 in this example) contains files and folders with content specific to the username configuration.
The \rsenc_eval directory is created by IPexpress the first time the core is generated and updated each time the
core is regenerated. A \<username> directory is created by IPexpress each time the core is generated and regen-
erated each time the core with the same file name is regenerated. A separate \<username> directory is gener-
ated for cores with different names, e.g. rsenc_core0, rsenc_core1, etc.
Running Functional Simulation
Simulation support for the Dynamic Block Reed-Solomon Encoder IP core is provided for Aldec Active-HDL (Ver-
ilog and VHDL) simulator, Mentor Graphics ModelSim simulator. The functional simulation includes a configuration-
specific behavioral model of the Dynamic Block Reed-Solomon Encoder IP core. The test bench sources stimulus
to the core, and monitors output from the core. The generated IP core package includes the configuration-specific
behavior model (<username>_beh.v) for func-tional simulation in the “Project Path” root directory. The simulation
scripts supporting ModelSim evaluation simulation is provided in 
\<project_dir>\rsenc_eval\<username>\sim\modelsim\scripts. The simulation script supporting
Aldec evaluation simulation is provided in 
\<project_dir>\rsenc_eval\<username>\sim\aldec\scripts. Both Modelsim and Aldec simulation is
supported via test bench files provided in
simulation are provided in the corresponding \models folder. Users may run the Aldec evaluation simulation by
doing the following:
1. Open Active-HDL.
2. Under the Tools tab, select Execute Macro.
3. Browse to folder \<project_dir>\rsenc_eval\<username>\sim\aldec\scripts and execute one of
Users may run the Modelsim evaluation simulation by doing the following:
1. Open ModelSim.
2. Under the File tab, select Change Directory and choose the folder 
3. 3. Under the Tools tab, select Execute Macro and execute the ModelSim “do” script shown.
Note: When the simulation completes, a pop-up window will appear asking “Are you sure you want to finish?”
Answer No to analyze the results (answering Yes closes ModelSim).
Synthesizing and Implementing the Core in a Top-Level Design
Synthesis support for the Dynamic Block Reed-Solomon Encoder IP core is provided for Mentor Graphics Preci-
sion or Synopsys Synplify. The Dynamic Block Reed-Solomon Encoder IP core itself is synthesized and is provided
in NGO format when the core is generated in IPexpress. Users may synthesize the core in their own top-level
design by instantiating the core in their top-level as described previously and then synthesizing the entire design
with either Synplify or Precision RTL Synthesis. The following text describes the evaluation implementation flow for
Windows platforms. The flow for Linux and UNIX platforms is described in the Readme file included with the IP
core. The top-level files <username>_top.v are provided in 
\<project_dir>\rsenc_eval\<username>\src\rtl\top. Push-button implementation of the reference
design is supported via Diamond or ispLEVER project files, <username>.syn, located in the following directory:
\<project_dir>\rsenc_eval\<username>\impl\(synplify or precision).
the "do" scripts shown.
<project_dir>\rsenc_eval\<username>\sim\modelsim\scripts.
\<project_dir>\rsenc_eval\testbench. Models required for
25 Dynamic Block Reed-Solomon Encoder User’s Guide
Figure 4-3
contains files and folders with content that
IP Core Generation