BD00IA5WEFJ-E2 ROHM Semiconductor, BD00IA5WEFJ-E2 Datasheet - Page 17

• Manufacturer Part Number: BD00IA5WEFJ-E2
• Description: Low Dropout Controllers - LDO LDO Reg Pos Variable Vltg 0.5A
• Manufacturer: ROHM Semiconductor

Specifications of BD00IA5WEFJ-E2

• Rohs: yes
• Input Voltage Max: 5.5 V
• Output Current: 0.5 A
• Load Regulation: 75 mV
• Output Type: Adjustable
• Number Of Outputs: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: HTSOP-8
• Input Voltage Min: 2.4 V
• Maximum Power Dissipation: 2110 mW
• Minimum Operating Temperature: - 25 C

Status of this document
The Japanese version of this document is formal specification. A customer may use this translation version only for a reference
to help reading the formal version.
If there are any differences in translation version of this document formal version takes priority.
TSZ22111･15･001
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
BDxxIA5WEFJ
(11) Testing on application boards
(12) Regarding input pin of the IC
(13) Ground Wiring Pattern.
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC’s power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic
diode or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change
the GND wiring pattern of any external components, either.
Parasitic element
Pin A
N P
+
N
GND
P
P substrate
P
+
Resistor
N
Pin A
Parasitic
element
Parasitic element
17/19
Pin B
N
P
+
C
B
N
E
GND
P
P substrate
Transistor (NPN)
P
+
N
GND
TSZ02201-0R6R0A600170-1-2
Other adjacent elements
Pin B
9.July.2012 Rev.001
B
C
E
GND
Datasheet
Parasitic
element