LS110GXS-2CF269C Lattice, LS110GXS-2CF269C Datasheet - Page 20

• Manufacturer Part Number: LS110GXS-2CF269C
• Description: LVDS Interface IC 10 Gbps PHY Physical Layer Transceiver, 1.3V
• Manufacturer: Lattice
• Type: LVCMOSr

Specifications of LS110GXS-2CF269C

• Data Rate: 10310 Mbps
• Operating Supply Voltage: 1.3 V, 2.5 V
• Maximum Power Dissipation: 1050 mW
• Maximum Operating Temperature: + 70 C
• Package / Case: BGA-269
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 126
• Supply Voltage - Max: 1.37 V, 2.63 V
• Supply Voltage - Min: 1.23 V, 2.37 V

Lattice Semiconductor
Output Pin Assignments and Descriptions
TX_D_N
TX_D_P
TX_LOCK
CK622OUT_N
CK622OUT_P
RX_CK_LV_P
RX_CK_LV_N
RX_D_LV_N[15], RX_D_LV_P[15],
RX_D_LV_N[14], RX_D_LV_P[14],
RX_D_LV_N[13], RX_D_LV_P[13],
RX_D_LV_N[12], RX_D_LV_P[12],
RX_D_LV_N[11], RX_D_LV_P[11],
RX_D_LV_N[10], RX_D_LV_P[10],
RX_D_LV_N[9], RX_D_LV_P[9],
RX_D_LV_N[8], RX_D_LV_P[8],
RX_D_LV_N[7], RX_D_LV_P[7],
RX_D_LV_N[6], RX_D_LV_P[6],
RX_D_LV_N[5], RX_D_LV_P[5],
RX_D_LV_N[4], RX_D_LV_P[4],
RX_D_LV_N[3], RX_D_LV_P[3],
RX_D_LV_N[2], RX_D_LV_P[2],
RX_D_LV_N[1],RX_D_LV_P[1],
RX_D_LV_N[0], RX_D_LV_P[0]
RX_LOCK
RX_D_RP_P
RX_D_RP_N
TX_FIFO_ERR
1. CMU mode only.
2. Based on RX_REF_CK_Enb
3. Operation above 10.3Gbps is not supported.
Pin Name
3
10 Gbps CML transmit data. See Figure 5.
TX PLL lock indicator:
TX LOCK = 1, internal TX_CLK locked to REF_CLK;
TX LOCK = 0, PLL is unlocked.
622 MHz LVDS clock output. Phase is adjustable
CMU or CDR clock.
LVDS clock output. Clock is source synchronous to the LVDS
receive, runs at 622MHz and is phase adjustable.
LVDS data output. See Figure 8.
Receiver PLL lock indicator. The PLL locks to
REF_CK/RX_REF_CK.
RX_LOCK = 1, receiver PLL frequency is within 300 ppm;
RX_LOCK = 0, receiver PLL frequency is larger than 450 ppm;
Frequency difference range is adjustable by
SC_LOCK_DIFF[1:0].
10 Gbps CML output, repeat data. This output repeats the data
at the RX_D_P/N inputs when RX_D_RP_Enb = 0. This output
can be used for diagnostic purposes and to evaluate the receiv-
ers limiting amplifier. These pins can be left unconnected if
unused.
FIFO error. 1 = error, 0 = normal operation.
2
Pin Description
20
1
and locks to
XPIO 110GXS Data Sheet
LVCMOS/
LVCMOS/
LVCMOS/
Function
LVDS/
LVDS/
LVDS/
CML/
CML/
Out
Out
Out
Out
Out
Out
Out
Out
BGA Ball #
Flip-chip
T10, U10
T11, U11
T12, U12
T13, U13
T14, U14
T15, U15
T16, U16
T17, U17
T1, U1,
T2, U2
T3, U3
T4, U4
T5, U5
T6, U6
T7, U7
T8, U8
M17
H14
G14
D7
R4
R5
U9
D6
K3
T9
L3