DS2155LB Maxim Integrated, DS2155LB Datasheet - Page 190

• Manufacturer Part Number: DS2155LB
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Device Interrupt Status (DISn). Causes all devices participating in the ESIB group to output their
interrupt status on the appropriate data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR1
register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Device Receive Loss-of-Sync (DRLOSn). Causes all devices participating in the ESIB group to output
their frame synchronization status on the appropriate data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of
the ESIBCR1 register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/User-Selected Status 1 (UST1n). Causes all devices participating in the ESIB group to output status or
alarms as selected by the ESI3SEL0 to ESI3SEL2 bits in the ESIBCR2 configuration register on the appropriate
data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR2 register
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/User-Selected Status 2 (UST2n). Causes all devices participating in the ESIB group to output status or
alarms as selected by the ESI4SEL0 to ESI4SEL2 bits in the ESIBCR2 configuration register on the appropriate
data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR2 register
DRLOSn
UST1n
UST2n
DISn
7
0
7
0
7
0
7
0
DRLOSn
UST1n
UST2n
DISn
ESIB1
Extended System Information Bus Register 1
B2h
ESIB2
Extended System Information Bus Register 2
B3h
ESIB3
Extended System Information Bus Register 3
B4h
ESIB4
Extended System Information Bus Register 4
B5h
6
0
6
0
6
0
6
0
DRLOSn
UST1n
UST2n
DISn
5
0
5
0
5
0
5
0
DRLOSn
UST1n
UST2n
DISn
4
4
4
4
0
0
0
0
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DRLOSn
UST1n
UST2n
DISn
3
0
3
0
3
0
3
0
DRLOSn
UST1n
UST2n
DISn
2
0
2
0
2
0
2
0
DRLOSn
UST1n
UST2n
DISn
1
0
1
0
1
0
1
0
DRLOSn
UST1n
UST2n
DISn
0
0
0
0
0
0
0
0