DS2155LB Maxim Integrated, DS2155LB Datasheet - Page 204

• Manufacturer Part Number: DS2155LB
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Table 34-B. ID Code Structure
Table 34-C. Device ID Codes
34.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers, the boundary scan register and the bypass register.
An optional test register, the identification register, has been included with the DS2155 design. It is used
with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
34.4 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital
I/O cells. It is n bits in length. See
34.5 Bypass Register
This is a single one-bit shift register used with the BYPASS, CLAMP, and HIGH-Z instructions that
provides a short path between JTDI and JTDO.
34.6 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
See
MSB
Version
Contact Factory
4 bits
DS2155
DS2156
DS21354
DS21554
DS21352
DS21552
Table 34-B
PART
and
Device ID
16 bits
Table 34-C
16-BIT ID
0010h
0019h
0005h
0003h
0004h
0002h
JEDEC
00010100001
for more information on bit usage.
Table 34-D
for cell bit locations and definitions.
204 of 238
LSB
1
1