DS2155LB Maxim Integrated, DS2155LB Datasheet - Page 63

• Manufacturer Part Number: DS2155LB
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 3/Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of
the chip. IDO is the LSB of a decimal code that represents the chip revision.
Bits 4 to 7/Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the DS2155 ID.
11.1 T1/E1 Status Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive Loss-of-Sync Condition (RLOS). Set when the DS2155 is not synchronized to the received data
stream.
Bit 1/Framer Receive Carrier-Loss Condition (FRCL). Set when 255 (or 2048 if E1RCR2.0 = 1) E1 mode or
192 T1 mode consecutive 0s have been detected at RPOSI and RNEGI.
Bit 2/Receive Unframed All-Ones (T1 Blue Alarm, E1 AIS) Condition (RUA1). Set when an unframed all 1s
code is received at RPOSI and RNEGI.
Bit 3/Receive Yellow Alarm Condition (RYEL) (T1 Only). Set when a Yellow Alarm is received at RPOSI and
RNEGI.
Bit 4/Receive Loss-of-Sync Clear Event (RLOSC). Set when the framer achieves synchronization; remains set
until read.
Bit 5/Framer Receive Carrier-Loss Clear Event (FRCLC). Set when the carrier loss condition at RPOSI and
RNEGI is no longer detected.
Bit 6/Receive Unframed All-Ones Clear Event (RUA1C). Set when the unframed all 1s condition is no longer
detected.
Bit 7/Receive Yellow Alarm Clear Event (RYELC) (T1 Only). Set when the receive Yellow Alarm condition is
no longer detected.
RYELC
ID7
7
1
7
0
RUA1C
ID6
IDR
Device Identification Register
0Fh
SR2
Status Register 2
18h
6
0
6
0
FRCLC
ID5
5
1
5
0
RLOSC
ID4
4
1
4
0
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RYEL
ID3
X
3
3
0
RUA1
ID2
X
2
2
0
FRCL
ID1
X
1
1
0
RLOS
ID0
X
0
0
0