DS2155LB Maxim Integrated, DS2155LB Datasheet - Page 21

• Manufacturer Part Number: DS2155LB
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Signal Description:
Signal Type:
Buffered clock that is used to clock data through the transmit-side formatter (i.e., either TCLK or RCLKI). This pin
is normally connected to TCLKI.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected
to TPOSO by connecting the LIUC pin high. TPOSI and TNEGI can be connected together in NRZ applications.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected
to TNEGO by connecting the LIUC pin high. TPOSI and TNEGI can be connected together in NRZ applications.
Signal Name:
Signal Description:
Signal Type:
Line interface transmit clock. Can be internally connected to TCLKO by connecting the LIUC pin high.
4.2 Receive Side
Signal Name:
Signal Description:
Signal Type:
T1 Mode: Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a
frame.
E1 Mode: Updated with the full E1 data stream on the rising edge of RCLK.
Signal Name:
Signal Description:
Signal Type:
T1 Mode: A 4kHz or 2kHz (ZBTSI) clock for the RLINK output.
E1 Mode: A 4kHz to 20kHz clock.
Signal Name:
Signal Description:
Signal Type:
1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer.
Signal Name:
Signal Description:
Signal Type:
A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Synchronous with RCLK
when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is
enabled. Useful for parallel-to-serial conversion of channel data.
Transmit Clock Output
Output
TPOSI
Transmit Positive-Data Input
Input
TNEGI
Transmit Negative-Data Input
Input
TCLKI
Transmit Clock Input
Input
RLINK
Receive Link Data
Output
RLCLK
Receive Link Clock
Output
RCLK
Receive Clock
Output
RCHCLK
Receive Channel Clock
Output
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