DS2282/87-22282-000 Maxim Integrated, DS2282/87-22282-000 Datasheet - Page 11

• Manufacturer Part Number: DS2282/87-22282-000
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2282/87-22282-000

• Supply Current (max): 30 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: SIL-30
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 5 V
• Part # Aliases: 90-22820-000

NOTES:
1. All of the registers in the DS2282 that count events will saturate at their maximum possible count; they do not
2. Values indicated in hexadecimal format.
3. All register read/written LSB first.
NAME
UASICR
BESICR
SESICR
CSLFICR
ESDCR
UEEER
UASDCR
BESDCR
SESDCR
CSLFDCR
VITR
RMSR
CR
roll over. For example, all the 16–bit registers stop at a count of 65,535. They do not roll over to zero and
continue counting.
ADDR
2A
2B
2C
2D
2E
29
36
2F
30
31
32
33
34
2,3
R/W
W
R
R
R
R
R
R
R
R
R
R
R
R
CLEARABLE
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
DESCRIPTION
UAS Interval Count Registers. A set of 96 16–bit registers
that contain the Unavailable Second counts for the previous
96 individual 15–minute periods. Most recent interval is read
first.
BES Interval Count Registers. A set of 96 16–bit registers
that contain the Bursty Errored Second counts for the pre-
vious 96 individual 15–minute periods. Most recent interval
is read first.
SES Interval Count Registers. A set of 96 16–bit registers
that contain the Severely Errored Second counts for the pre-
vious 96 individual 15–minute periods. Most recent interval
is read first.
CSS & LOFC Interval Count Registers. A set of 96 16–bit
registers that contain the Controlled Slip and Loss Of Frame
counts for the previous 96 individual 15–minute periods. The
8–bit CSS count is the LSB and the 8–bit LOFC count is in
the MSB. Most recent interval is read first.
ES Day Count Registers. A 16–bit register that counts the
number of Errored Seconds in the previous 24–hour period.
User ESF Error Event Register. 16–bit register that mimics
the ESFEER for user access.
UAS Day Count Registers. A 16–bit register that counts
the number of Unavailable Seconds in the previous 24–hour
period.
BES Day Count Registers. A 16–bit register that counts
the number of Bursty Errored Seconds in the previous
24–hour period.
SES Day Count Registers. A 16–bit register that counts the
number of Severely Errored Seconds in the previous
24–hour period.
CSS & LOFC Day Count Registers. A 16–bit register that
counts the number of Controlled Slip Seconds and Loss Of
Frames in the previous 24–hour period. The 8–bit CSS
count is in the LSB and the 8–bit LOFC count is in the MSB.
Valid Interval Total Register. An 8–bit register that indi-
cates the number of valid 15–minute intervals in the previous
24–hour period.
Request Message Status Register. An 8–bit register that
indicates which (if any) request message is being received.
Control Register. An 8–bit register that selects which ad-
dress the DS2282 will respond to.
022798 11/22
DS2282