DS2282/87-22282-000 Maxim Integrated, DS2282/87-22282-000 Datasheet - Page 16

• Manufacturer Part Number: DS2282/87-22282-000
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS2282/87-22282-000

• Supply Current (max): 30 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: SIL-30
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 5 V
• Part # Aliases: 90-22820-000

Day Count Registers
The day count registers count the number of events that
have occurred in the previous 24 hour period. There are
five separate day count registers. They are:
Each of these current interval registers are 16 bits in
length. Please see “54016 Definitions” for definitions of
ES, UAS, BES, SES, CSS, and LOFC.
VITR: Valid Interval Total Register (32).
register that counts the number of 15 minute intervals
since the last reset. Hence, it has a maximum count of
96.
RMSR: Request Message Status Register
(33).
quest maintenance message has been received. If a re-
quest maintenance message is received, the INT pin
will be asserted (transitions low). The RMSR will be
cleared when read. This indicates to an external con-
troller that a request has been received and is being pro-
cessed. The INT pin will return high as soon as the
RMSR is accessed. There are currently 15 request
messages defined.
RM7
RM0
CR: Control Register (34).
selects whether the DS2282 will respond to address A
(or Z) or address B (or Y). The default is for the DS2282
to respond only to address A (or Z). The user can set the
DS2282 to respond address B (or Y) by setting the AD
DS2282
022798 16/22
(MSB)
RM7
ESDCR (2D)
UASDCR (2E) counts Unavailable Seconds (UAS)
BESDCR (2F) counts Bursty Errored Seconds (BES)
SESDCR (30) counts Severely Errored Seconds
CSLFDCR (31) counts Controlled Slip Seconds (CSS)
An 8–bit register that indicates which (if any) re-
RM6
RM5
MSB of the request message
LSB of the request message
counts Errored Seconds (ES)
(SES)
and Loss Of Frame Counts (LOFC)
RM4
RM3
An 8–bit register that
RM2
RM1
An 8–bit
RM0
(LSB)
bit to a one. In addition, CR allows the user to send an all
one’s sequence FFh or LAPD idel code 7Eh.
AD
ICS
54016 DEFINITIONS
Errored Seconds (ES): A one–second period with ei-
ther:
Severely Errored Seconds (SES): A one–second peri-
od with either:
Unavailable Seconds (UAS): A one–second period in
which an unavailable signal state is present. In counting
UAS, the initial period of 10 consecutive SES’s is in-
cluded in the count whereas the final 10 seconds of 10
consecutive non–SES’s which removes the unavailable
signal state is not included in the count. During UAS’s,
neither ES, or SES, or BES, are counted. Refer to
“Monitor Registers” for a more detailed description of
UAS.
Unavailable Signal State: An unavailable signal state
is declared when 10 consecutive SESs have been re-
ceived.
cleared when 10 consecutive non–SES events have oc-
curred.
Controlled Slip Seconds (CSS): A one–second period
with one or more controlled slips. A controlled slip is the
deletion or replication of a DS1 frame. Indications of
controlled slips are input to the DS2282 via the SLIP pin.
If indications of controlled slips are not available, the
SLIP pin should be tied low.
(MSB)
a. one or more CRC–6 error events or
b. one or more OOF events or
c. one or more controlled slips.
a. 320 or more CRC–6 error events or
b. one or more OOF events.
0
0
An unavailable signal state is considered
Address Select Bit. Set to a one to re-
spond to address B (or Y)
Idle Code Select
0 = FFh
1 = 7Eh
0
0
0
0
ICS
(LSB)
AD