XRT83SH314ES Exar, XRT83SH314ES Datasheet - Page 19

• Manufacturer Part Number: XRT83SH314ES
• Description: Peripheral Drivers & Components - PCIs 14 CHT1/E1LIU SH
• Manufacturer: Exar

Specifications of XRT83SH314ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 1.0.4
F
To reduce system noise and power consumption, the XRT83SH314 offers an ALL T1/E1 mode. Since most
line card designs are configured to operate in T1 or E1 only, the LIU can be selected to shut off the timing
references for the mode not being used by programming the appropriate global register. By default the ALL
T1/E1 mode is enabled (ALLT1/E1 bit = "0"). If the LIU is configured for T1, all E1 clock references and the
8kHz reference are shut off internally to the chip. This reduces the amount of internal clocks switching within
the LIU, hence reducing noise and power consumption. In E1 mode, the T1 clock references are internally
shut off, however the 8kHz reference is available. To disable this feature, the ALLT1/E1 bit must be set to a "1"
in the appropriate global register.
The receive path of the XRT83SH314 LIU consists of 14 independent T1/E1/J1 receivers. The following
section describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A
simplified block diagram of the receive path is shown in
F
1.1
2.0 RECEIVE PATH LINE INTERFACE
IGURE
IGURE
RPOS
RNEG
RCLK
2. S
3. S
ALL T1/E1 Mode
Input Clock
IMPLIFIED
IMPLIFIED
HDB3/B8ZS
Decoder
B
B
LOCK
LOCK
Synthesizer
MCLKE1Nout
MCLKT1Nout
MCLKE1out
D
MCLKT1out
D
Clock
8kHzOUT
IAGRAM OF THE
IAGRAM OF THE
Attenuator
Rx Jitter
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
Programmable
Programmable
C
R
Reference
1.544MHz
2.048MHz
LOCK
ECEIVE
Clock & Data
Internal
Recovery
15
S
Figure
YNTHESIZER
P
ATH
3.
8kHz
2.048MHz
2.048/4.096/8.192/16.384 MHz
1.544Mhz
1.544/3.088/6.176/12.352MHz
Peak Detector
& Slicer
XRT83SH314
RTIP
RRING