XRT83SH314ES Exar, XRT83SH314ES Datasheet - Page 29

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XRT83SH314ES

Manufacturer Part Number
XRT83SH314ES
Description
Peripheral Drivers & Components - PCIs 14 CHT1/E1LIU SH
Manufacturer
Exar
Datasheet

Specifications of XRT83SH314ES

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
REV. 1.0.4
The transmit path of the XRT83SH314 LIU consists of 14 independent T1/E1/J1 transmitters. The following
section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A
simplified block diagram of the transmit path is shown in
F
In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG has
no function and can be left unconnected. The XRT83SH314 can be programmed to sample the inputs on
either edge of TCLK. By default, data is sampled on the falling edge of TCLK. To sample data on the rising
edge of TCLK, set TCLKE to "1" in the appropriate global register.
transmit input data sampled on the falling edge of TCLK.
data sampled on the rising edge of TCLK. The timing specifications are shown in
F
3.0 TRANSMIT PATH LINE INTERFACE
3.1
IGURE
IGURE
TPOS
TNEG
TCLK
15. S
16. T
TPOS
TNEG
TCLK
TCLK/TPOS/TNEG Digital Inputs
or
RANSMIT
IMPLIFIED
HDB3/B8ZS
Encoder
D
B
ATA
LOCK
S
AMPLED ON
D
IAGRAM OF THE
Attenuator
Tx Jitter
F
ALLING
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
T
SU
T
RANSMIT
E
Control
Timing
DGE OF
25
Figure
P
Figure 17
ATH
TCLK
T
HO
15.
Tx Pulse Shaper
& Pattern Gen
TCLK
is a timing diagram of the transmit input
R
Figure 16
Table
TCLK
Line Driver
is a timing diagram of the
F
6.
XRT83SH314
TTIP
TRING

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