XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 27

• Manufacturer Part Number: XRT83VSH28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
• Manufacturer: Exar

Specifications of XRT83VSH28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 2.0.0
The XRT83VSH28 supports both G.775 or ETSI-300-233 RLOS detection scheme.
In G.775 mode, RLOS is declared when the received signal is less than 375mV for 32 consecutive pulse
periods (typical). The device clears RLOS when the receive signal achieves 12.5% ones density with no more
than 15 consecutive zeros in a 32 bit sliding window and the signal level exceeds 425mV (typical).
In ETSI-300-233 mode the device declares RLOS when the input level drops below 375mV (typical) for more
than 2048 pulse periods (1msec).
The device exits RLOS when the input signal exceeds 425mV (typical) and has transitions for more than 32
pulse periods with 12.5% ones density with no more than 15 consecutive zero’s in a 32 bit sliding window.
ETSI-300-233 RLOS detection method is only available in Host mode.
By enabling the extended loss of signal by programming the appropriate channel register, the digital RLOS is
extended to count 4,096 consecutive zeros before declaring RLOS. By default, EXLOS is disabled and RLOS
operates in normal mode.
The XRT83VSH28 adheres to the ITU-T G.775 specification for an all ones pattern. The AIS is set to "1" if the
incoming signal has 2 or less zeros in a 512-bit window. AIS will clear when the incoming signal has 3 or more
zeros in the 512-bit window.
The purpose of the FIFO limit status is to indicate when the Read and Write FIFO pointers are within a pre-
determined range (over-flow or under-flow indication). The FLSD is set to "1" if the FIFO Read and Write
Pointers are within ±3-Bits.
The LIU contains 8 independent, 16-bit LCV counters. When the counters reach full-scale, they remain
saturated at FFFFh until they are reset globally or on a per channel basis. For performance monitoring, the
counters can be updated globally or on a per channel basis to place the contents of the counters into holding
registers. The LIU uses an indirect address bus to access a counter for a given channel. Once the contents of
the counters have been placed in holding registers, they can be individually read out 8-bits at a time according
to the BYTEsel bit in the appropriate global register. By default, the LSB is placed in the holding register until
the BYTEsel is pulled "High" where upon the MSB will be placed in the holding register for read back. Once
both bytes have been read, the next channel may be selected for read back.
By default, the LVC/OFD will be set to a "1" if the receiver is currently detecting line code violations or
excessive zeros for HDB3. In AMI mode, the LCVD will be set to a "1" if the receiver is currently detecting
bipolar violations or excessive zeros. However, if the LIU is configured to monitor the 16-bit LCV counter by
programming the appropriate global register, the LCV/OFD will be set to a "1" if the counter saturates.
The receive path has a dedicated jitter attenuator that reduces phase and frequency jitter in the recovered
clock. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit.
If the LIU is used for line synchronization (loop timing systems), the JA should be enabled. When the Read and
Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the jitter
attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this condition
occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer’s position is outside the 2-
Bit window. The bandwidth is programmable to either 10Hz or 1.5Hz (1.5Hz automatically selects the 64-Bit
FIFO depth). The JA has a clock delay equal to ½ of the FIFO bit depth.
N
2.3
2.2.3.1
2.2.3.2
2.2.3.3
2.2.3.4
2.2.3.5
OTE
: If the LIU is used in a multiplexer/mapper application where stuffing bits are typically removed, the transmit path has
a dedicated jitter attenuator to smooth out the gapped clock. See the Transmit Section of this datasheet.
Receive Jitter Attenuator
RLOS (Receiver Loss of Signal)
EXLOS (Extended Loss of Signal)
AIS (Alarm Indication Signal)
FLSD (FIFO Limit Status Detection)
LCVD (Line Code Violation Detection)
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
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XRT83VSH28