XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 52

• Manufacturer Part Number: XRT83VSH28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
• Manufacturer: Exar

Specifications of XRT83VSH28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
In PowerPC mode the active signals are ADDR[7:0], DATA[7:0], CS, R/W (Intel WR), WE (Intel RD), RDY and
PCLK. In this mode all input signals are sampled by the PCLK. For all inputs minimum setup time is 4ns and
minimum hold time is 3ns. Maximum PCLK frequency is 50 MHz.
A READ cycle starts with R/W being 'HIGH' and assertion of CS, address is assumed to be stable at this time
since CS is usually derived from the decoding the address bus.
Operation with wait-states is possible, provided the wait is longer than the minimum cycle time. Use of RDY is
recommended for timing efficiency since the read cycle time can vary depending on the internal address location
being accessed.
WRITE operation is identical to the READ operation except that the cycle starts with R/W being 'LOW', followed
by CS assertion further followed by assertion of WE. Data to be written at the addressed location should be valid
on the data bus at the time WE is asserted. WE should remain asserted until RDY is asserted by the device.
Following RDY assertion WE and CS may be de-asserted.
F
Note: The value for t25 through t38 can be found in
Table 16
5.6
IGURE
Timing
t23
t24
t25
34. P
PowerPC 403 Synchronous Mode:
Power PC403 Mode Timing - Write Operation
R/W "Low" to rising edge of PCLK set-up time (Write Operation)
CS "Low" to rising edge of PCLK set-up time
Rising edge of PCLK to RDY "Low" delay
OWER
Test Conditions: TA = 25°C, VCC = 3.3V±5% and 1.8V±5%, unless otherwise specified
PC 403 M
ADDR[7:0]
D[7:0]
PClk
RDY
R/W
WE
CS
ODE
T
1
IMING
Description
2
- W
t24
t23
RITE
3
Table 16
O
PERATION
4
49
.
8 PClk Cycles
5
6
7
Min.
8
5
5
4
t25
9
Typ.
10
-
-
-
Max.
-
-
-
REV. 2.0.0
Units
ns
ns
ns