XRT83VSH28ES Exar, XRT83VSH28ES Datasheet - Page 66

• Manufacturer Part Number: XRT83VSH28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH (low cost version)
• Manufacturer: Exar

Specifications of XRT83VSH28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
R
5.9
EGISTER
0
B
X
D7
D6
D5
D4
D3
D2
D1
D0
Global Control Registers
IT
80
A
#
H
DDRESS
Reserved
SRESET
RCLKE
ATAOS
TCLKE
SR/DR
DATAP
N
T
GIE
ABLE
AME
30: M
Single-rail/Dual-rail Select: Writing a “1” to this bit configures
all 4channels in the XRT83VSH28 to operate in the Single-rail
mode.
Writing a “0” configures the XRT83VSH28 to operate in Dual-
rail mode.
Automatic Transmit All Ones Upon RLOS: Writing a “1” to
this bit enables the automatic transmission of All "Ones" data
to the line for the channel that detects an RLOS condition.
Writing a “0” disables this feature.
Receive Clock Edge: Writing a “1” to this bit selects receive
output data of all channels to be updated on the negative edge
of RCLK.
Wring a “0” selects data to be updated on the positive edge of
RCLK.
Transmit Clock Edge: Writing a “0” to this bit selects transmit
data at TPOS_n/TDATA_n and TNEG_n/CODES_n of all
channels to be sampled on the falling edge of TCLK_n.
Writing a “1” selects the rising edge of the TCLK_n for sam-
pling.
DATA Polarity: Writing a “0” to this bit selects transmit input
and receive output data of all channels to be active “High”.
Writing a “1” selects an active “Low” state.
Global Interrupt Enable: Writing a “1” to this bit globally
enables interrupt generation for all channels.
Writing a “0” disables interrupt generation.
Software Reset  P Registers: Writing a “1” to this bit longer
than 10µs initiates a device reset through the microprocessor
interface. All internal circuits are placed in the reset state with
this bit set to a “1” except the microprocessor register bits.
ICROPROCESSOR
R
63
EGISTER
F
UNCTION
0
X
80
H
, B
IT
D
ESCRIPTION
R
EGISTER
T
R/W
R/W
R/W
R/W
R/W
R/W
R/W
YPE
REV. 2.0.0
R
V
ALUE
ESET
0
0
0
0
0
0
0
0