89H32NT24BG2ZBHLG IDT, 89H32NT24BG2ZBHLG Datasheet - Page 10

• Manufacturer Part Number: 89H32NT24BG2ZBHLG
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H32NT24BG2ZBHLG

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes
• Part # Aliases: IDT89H32NT24BG2ZBHLG

IDT 89HPES32NT24AG2 Data Sheet
CLKMODE[1:0]
STK0CFG[1:0]
STK1CFG[1:0]
STK2CFG[4:0]
STK3CFG[4:0]
SWMODE[3:0]
GCLKFSEL
RSTHALT
Signal
Signal
PERSTN
Type
Type
I
I
I
I
I
I
I
I
I
Stack 0 Configuration. These pins select the configuration of stack 0.
Stack 1 Configuration. These pins select the configuration of stack 1.
Stack 2 Configuration. These pins select the configuration of stack 2.
Stack 3 Configuration. These pins select the configuration of stack 3.
Clock Mode. These signals determine the port clocking mode used by ports of the
device.
Global Clock Frequency Select. These signals select the frequency of the GCLKP
and GCLKN signals.
0x0 100 MHz
0x1 125 MHz
Fundamental Reset. Assertion of this signal resets all logic inside the device.
Reset Halt. When this signal is asserted during a switch fundamental reset sequence,
the switch remains in a quasi-reset state with the Master and Slave SMBuses active.
This allows software to read and write registers internal to the device before normal
device operation begins. The device exits the quasi-reset state when the RSTHALT bit
is cleared in the SWCTL register by an SMBus master.
Switch Mode. These configuration pins determine the switch operating mode.
0x0 - Single partition
0x1 - Single partition with Serial EEPROM initialization
0x2 - Single partition with Serial EEPROM Jump 0 initialization
0x3 - Single partition with Serial EEPROM Jump 1 initialization
0x4 through 0x7 - Reserved
0x8 - Single partition with reduced latency
0x9 - Single partition with Serial EEPROM initialization and reduced latency
0xA - Multi-partition with Unattached ports
0xB - Multi-partition with Unattached ports and I
0xC - Multi-partition with Unattached ports and Serial EEPROM initialization
0xD - Multi-partition with Unattached ports with I
0xE - Multi-partition with Disabled ports
0xF - Multi-partition with Disabled ports and Serial EEPROM initialization
These pins should be static and not change following the negation of PERSTN.
Table 6 Stack Configuration Pins
ization
Table 7 System Pins
10 of 38
Name/Description
Name/Description
2
2
C Reset
C Reset and Serial EEPROM initial-
March 14, 2012