89H32NT24BG2ZBHLG IDT, 89H32NT24BG2ZBHLG Datasheet - Page 4

• Manufacturer Part Number: 89H32NT24BG2ZBHLG
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H32NT24BG2ZBHLG

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes
• Part # Aliases: IDT89H32NT24BG2ZBHLG

SMBus Interface
PES32NT24AG2, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default
configuration register values of the PES32NT24AG2 to be overridden following a reset with values programmed in an external serial EEPROM. The
master interface is also used by an external Hot-Plug I/O expander.
SSMBADDR2 pins. As shown in Figure 2, the master and slave SMBuses may only be used in a split configuration. In the split configuration, the
master and slave SMBuses operate as two independent buses; thus, multi-master arbitration is not required. The SMBus master interface does not
support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the SMBus lines that connect to the serial EEPROM
and I/O expander slaves.
Hot-Plug Interface
device, the PES32NT24AG2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface.
Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES32NT24AG2 generates an SMBus transac-
tion to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is
received on the IOEXPINTN input pin (alternate function of GPIO) of the PES32NT24AG2. In response to an I/O expander interrupt, the
PES32NT24AG2 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
outputs, or alternate functions. All GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus
slave interface, or serial configuration EEPROM.
Pin Description
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
The PES32NT24AG2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the
Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has SSMBADDR1 and
The PES32NT24AG2 supports PCI Express Hot-Plug on each downstream port (ports 1 through 23). To reduce the number of pins required on the
The PES32NT24AG2 provides 9 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
The following tables list the functions of the pins provided on the PES32NT24AG2. Some of the functions listed may be multiplexed onto the same
IDT 89HPES32NT24AG2 Data Sheet
Switch
Figure 2 Split SMBus Interface Configuration
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
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EEPROM
Processor
SMBus
Serial
Master
...
Expander
Hot-Plug
I/O
Devices
SMBus
Other
March 14, 2012