89H32NT24BG2ZBHLG IDT, 89H32NT24BG2ZBHLG Datasheet - Page 11

• Manufacturer Part Number: 89H32NT24BG2ZBHLG
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H32NT24BG2ZBHLG

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes
• Part # Aliases: IDT89H32NT24BG2ZBHLG

Pin Characteristics
IDT 89HPES32NT24AG2 Data Sheet
Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to
appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, floating
pins can cause a slight increase in power consumption. Unused Serdes (Rx and Tx) pins should be left floating. Finally, No Connection pins
should not be connected.
JTAG_TRST_N
JTAG_TCK
JTAG_TDO
JTAG_TMS
JTAG_TDI
Signal
REFRES[7:0]
REFRESPLL
V
V
V
Signal
V
DD
V
DD
DD
DD
DD
V
CORE
PEHA
PETA
SS
PEA
I/O
Type
O
Type
I
I
I
I
—
—
—
—
—
—
—
—
Table 9 Power, Ground, and SerDes Resistor Pins
JTAG Clock. This is an input test clock used to clock the shifting of data into or out of
the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system
clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG
Controller.
JTAG Data Output. This is the serial data shifted out from the boundary scan logic or
JTAG Controller. When no data is being shifted out, this signal is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the boundary
scan logic or JTAG Controller.
JTAG Reset. This active low signal asynchronously resets the boundary scan logic
and JTAG TAP Controller. An external pull-up on the board is recommended to meet
the JTAG specification in cases where the tester can access this signal. However, for
systems running in functional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
External Reference Resistor. Reference for the corresponding SerDes
bias currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should
be connected from this pin to ground and isolated from any source of noise
injection. Each bit of this signal corresponds to a SerDes quad, e.g.,
REFRES[5] is the reference resistor for SerDes quad 5.
PLL External Reference Resistor. Provides a reference for the PLL bias
currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should be
connected from this pin to ground and isolated from any source of noise
injection.
Core V
I/O V
PCI Express Analog Power. Serdes analog power supply (1.0V).
PCI Express Analog High Power. Serdes analog power supply (2.5V).
PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
Ground.
DD.
DD.
LVTTL I/O buffer power supply (3.3V).
Table 8 Test Pins
Power supply for core logic (1.0V).
11 of 38
Name/Description
Name/Description
March 14, 2012