74LVC2G38DP-G NXP Semiconductors, 74LVC2G38DP-G Datasheet - Page 3

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74LVC2G38DP-G

Manufacturer Part Number
74LVC2G38DP-G
Description
Logic Gates 3.3V DUAL 2-IN NAND BUF OPEN-D
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC2G38DP-G

Product Category
Logic Gates
Rohs
yes
Product
NAND
Logic Family
LVC
Number Of Gates
2
Number Of Lines (input / Output)
2 / 1
Low Level Output Current
32 mA
Propagation Delay Time
2.1 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-505
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Number Of Output Lines
1
Factory Pack Quantity
3000
Part # Aliases
74LVC2G38DP,125
NXP Semiconductors
5. Functional diagram
6. Pinning information
74LVC2G38
Product data sheet
Fig 1.
Fig 3.
Fig 4.
Logic symbol
Functional diagram (one gate)
Pin configuration SOT505-2 and SOT765-1
GND
1A
1B
2Y
6.1 Pinning
1
2
3
4
1A
1B
2A
2B
74LVC2G38
001aah753
001aab829
1Y
2Y
8
7
6
5
All information provided in this document is subject to legal disclaimers.
V
1Y
2B
2A
CC
A
B
Rev. 10 — 28 June 2012
Fig 2.
Fig 5.
mnb131
IEC logic symbol
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
GND
Y
GND
Dual 2-input NAND gate; open drain
1A
1B
2Y
Transparent top view
74LVC2G38
1
2
3
4
001aah754
&
&
001aab830
74LVC2G38
8
7
6
5
V
1Y
2B
2A
CC
© NXP B.V. 2012. All rights reserved.
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