LED7708 STMicroelectronics, LED7708 Datasheet - Page 39

• Manufacturer Part Number: LED7708
• Description: LED Lighting Drivers 16 Ch 85mA LED 3.6 to 36V 250kHz
• Manufacturer: STMicroelectronics

Specifications of LED7708

• Rohs: yes

LED7708
8.6
8.6.1
The content of the internal registers, except the read-only bits of DEVCFG0 and DEVCFG1
(i.e. CFP, OVRS, OVFW and EDMI), is not affected when the DEN bit is cleared.
Dimming options
The brightness of the LEDs connected to the output channels can be basically controlled in
two ways, depending on the status of the GSME bit of the DEVCFG1 register:
●
●
In practice, a third way to control the brightness of the LEDs should rely on an intensive use
of the CHSEL register by the host controller. The direct control of the CHSEL register,
combined with either the group dimming or the grayscale dimming, allows the user to
implement particular dimming algorithms.
Once the dimming control mode has been chosen through the GSME bit, the source of the
clock for the PWM generation (grayscale clock) must be selected. The LED7708 can use
either an external clock source or its internal high-frequency oscillator.
Internal dimming oscillator
The LED7708 has a programmable oscillator dedicated to the dimming circuitry.
The output clock is provided at the GSCK pin for the slave devices. If the FOSC pin is forced
high, the oscillator is turned off and the GSCK pin becomes the grayscale clock input.
Table 20.
The oscillator frequency is simply set by connecting a resistor between the FOSC pin and
ground:
Equation 14
FOSC pin setting
Resistor to GND
Group dimming mode (GSME=0): common dimming performed by using the brightness
value received through the serial interface and stored in the BRT01 register: all the
channels have the same PWM duty cycle;
Grayscale dimming mode (GSME=1): independent PWM dimming on each channel
performed by loading the BRT01:BRT16 brightness registers.
High (to LDO3)
Warning:
FOSC pin setting options
In order to prevent damage to the device or to the external
circuitry, some bits of DEVCFG0 and DEVCFG1 registers
(CRS, SDMS and DSYS) are locked when DEN is high.
Active (4 MHz-25 MHz)
Doc ID 022698 Rev 1
Oscillator
OFF
f
GSCK
=
R
K
FOSC
OSC
Recommended operating conditions
Grayscale clock output
Grayscale clock input
GSCK pin function
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