P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet

P5010NXN1QMB

Manufacturer Part Number

P5010NXN1QMB

Description

Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0

Manufacturer

Freescale Semiconductor

Datasheet

1.P5010NXN1QMB.pdf (163 pages)

Specifications of P5010NXN1QMB

Rohs

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Freescale Semiconductor

Data Sheet: Technical Data

P5020/P5010 QorIQ

Integrated Processor

Hardware Specifications

The P5020 and P5010 QorIQ integrated communication

processor combines Power Architecture® processor cores

with high-performance data path acceleration logic and

network and peripheral bus interfaces required for

networking, telecom/datacom, wireless infrastructure, and

aerospace applications.

This chip can be used for combined control, data path, and

application layer processing in routers, switches, base station

controllers, and general-purpose embedded computing. Its

high level of integration offers significant performance

benefits compared to multiple discrete devices while also

greatly simplifying board design.

Unless otherwise stated, all parameters within this document

apply to both the P5020 and the P5010.

The chip includes the following function and features:

• Two e5500 Power Architecture cores (one on the P5010)

• CoreNet fabric supporting coherent and non-coherent

• 2-Mbyte CoreNet platform cache with ECC (one on the

• One 10-Gigabit Ethernet (XAUI) controller

• Five 1-Gigabit Ethernet controllers

• Two 64-bit DDR3/3L SDRAM memory controllers with

• Multicore programmable interrupt controller (MPIC)

• Four I

• Four 2-pin UARTs or two 4-pin UARTs

Freescale reserves the right to change the detail specifications as may be required

to permit improvements in the design of its products.

– Each core has a backside 512-Kbyte L2 Cache with ECC

– Three levels of instructions: User, Supervisor, and

– Independent boot and reset

– Secure boot capability

transactions amongst CoreNet endpoints

P5010)

– 1 Gb/s SGMII, 2.5 Gb/s SGMII and RGMII interfaces

ECC (one on the P5010)

Hypervisor

C controllers

NOTE

• Two 4-channel DMA engines

• Enhanced local bus controller (eLBC)

• Four PCI Express 2.0 controllers/ports

• Two Serial RapidIO® controllers/ports (sRIO port)

• Two serial ATA (SATA) 2.0 controllers

• Enhanced secure digital host controller (SD/MMC)

• Enhanced serial peripheral interfaces (eSPI)

• 2× full-speed USB 2.0 controllers with integrated PHYs

• RAID 5 and 6 storage accelerator with support for

v1.3-compliant with features of v2.1

end-to-end data protection information

P5020/P5010

Document Number: P5020EC

FC-PBGA–1295

37.5 mm × 37.5 mm

Rev. 0, 03/2013

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