P5010NXN1QMB Freescale Semiconductor, P5010NXN1QMB Datasheet - Page 107

• Manufacturer Part Number: P5010NXN1QMB
• Description: Processors - Application Specialized P5010 Ext Tmp NoEnc 1600/1200 r2.0
• Manufacturer: Freescale Semiconductor

Specifications of P5010NXN1QMB

• Rohs: yes

The characteristics of the clock signals are as follows:
2.20.2.2
The DC level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect
the clock driver chip and SerDes reference clock inputs, as described below:
Freescale Semiconductor
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SD_REF_CLKn
SD_REF_CLKn
The SerDes transceivers core power supply voltage requirements (SV
“Recommended Operating
The SerDes reference clock receiver reference circuit structure is as follows:
— The SD_REF_CLKn and SD_REF_CLKn are internally AC-coupled differential inputs as shown in
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and
The maximum average current requirement also determines the common mode voltage range.
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V ÷ 50 = 8 mA)
— If the device driving the SD_REF_CLKn and SD_REF_CLKn inputs cannot drive 50 Ω to SGND DC or the drive
The input amplitude requirement is described in detail in the following sections.
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or
— For an external DC-coupled connection, as described in
Figure 38. Differential Reference Clock Input DC Requirements (External DC-Coupled)
Each differential clock input (SD_REF_CLKn or SD_REF_CLKn) has on-chip 50-Ω termination to SGND
followed by on-chip AC-coupling.
single-ended mode descriptions below for detailed requirements.
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input
is AC-coupled on-chip.
while the minimum common mode input level is 0.1 V above SGND. For example, a clock with a 50/50 duty cycle
can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such
that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode
voltage at 400 mV.
strength of the clock driver chip exceeds the maximum input current limitations, it must be AC-coupled off-chip.
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
Characteristics,” the maximum average current requirements sets the requirement for average voltage (common
mode voltage) as between 100 mV and 400 mV.
for DC-coupled connection scheme.
DC Level Requirement for SerDes Reference Clocks
P5020/P5010 QorIQ Integrated Processor Hardware Specifications, Rev. 0
200 mV < Input Amplitude or Differential Peak < 800 mV
Conditions.”
Figure 38
Section 2.20.2.1, “SerDes Reference Clock Receiver
shows the SerDes reference clock input requirement
DD
) are as specified in
100 mV
Electrical Characteristics
Section 2.1.2,
<
Vcm
Vmax
Vmin
<
<
>
400 mV
800 mV
0 V
Figure
37.
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