79RC32K438-233BB IDT, 79RC32K438-233BB Datasheet - Page 16

• Manufacturer Part Number: 79RC32K438-233BB
• Description: Processors - Application Specialized
• Manufacturer: IDT

Specifications of 79RC32K438-233BB

• Part # Aliases: IDT79RC32K438-233BB

IDT 79RC32438
MDATA[7]
MDATA[8]
MDATA[11:9]
MDATA[12]
MDATA[15:13]
Signal
Boot Device Width. This field specifies the width of the boot device (i.e., Device 0).
0x0 - 8-bit boot device width
0x1 - 16-bit boot device width
Reset Mode. This bit specifies the length of time the RSTN signal is driven.
0x0 - Normal reset: RSTN driven for minimum of 4096 clock cycles
0x1 - reserved
PCI Mode. This bit controls the operating mode of the PCI bus interface. The initial
value of the EN bit in the PCIC register is determined by the PCI mode.
0x0 - Disabled (EN initial value is zero)
0x1 - PCI satellite mode with PCI target not ready (EN initial value is one)
0x2 - PCI satellite mode with suspended CPU execution (EN initial value is one)
0x3 - PCI host mode with external arbiter (EN initial value is zero)
0x4 - PCI host mode with internal arbiter using fixed priority arbitration algorithm
0x5 - PCI host mode with internal arbiter using round robin arbitration algorithm
0x6 - reserved
0x7 - reserved
Disable Watchdog Timer. When this bit is set, the watchdog timer is disabled follow-
ing a cold reset.
0x0 - Watchdog timer enabled
0x1 - Watchdog timer disabled
Reserved. These pins must be driven low during boot configuration.
Table 3 Boot Configuration Encoding (Part 2 of 2)
(EN initial value is zero)
(EN initial value is zero)
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Name/Description
May 25, 2004