79RC32K438-233BB IDT, 79RC32K438-233BB Datasheet - Page 6

• Manufacturer Part Number: 79RC32K438-233BB
• Description: Processors - Application Specialized
• Manufacturer: IDT

Specifications of 79RC32K438-233BB

• Part # Aliases: IDT79RC32K438-233BB

IDT 79RC32438
DDRVREF
DDRWEN
PCI Bus
PCIAD[31:0]
PCICBEN[3:0]
PCICLK
PCIDEVSELN
PCIFRAMEN
PCIGNTN[3:0]
PCIIRDYN
PCILOCKN
PCIPAR
PCIPERRN
Signal
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
DDR Voltage Reference. SSTL_2 DDR voltage reference generated by an
external source.
DDR Write Enable. DDR write enable is asserted during DDR write transac-
tions.
PCI Multiplexed Address/Data Bus. Address is driven by a bus master during
initial PCIFRAMEN assertion. Data is then driven by the bus master during
writes or by the bus target during reads.
PCI Multiplexed Command/Byte Enable Bus. PCI command is driven by the
bus master during the initial PCIFRAMEN assertion. Byte enable signals are
driven by the bus master during subsequent data phase(s).
PCI Clock. Clock used for all PCI bus transactions.
PCI Device Select. This signal is driven by a bus target to indicate that the tar-
get has decoded the address as one of its own address spaces.
PCI Frame. Driven by a bus master. Assertion indicates the beginning of a bus
transaction. Negation indicates the last data.
PCI Bus Grant.
In PCI host mode with internal arbiter:
The assertion of these signals indicates to the agent that the internal RC32438
arbiter has granted the agent access to the PCI bus.
In PCI host mode with external arbiter:
PCIGNTN[0]: asserted by an external arbiter to indicate to the RC32438 that
access to the PCI bus has been granted.
PCIGNTN[3:1]: unused and driven high.
In PCI satellite mode:
PCIGNTN[0]: This signal is asserted by an external arbiter to indicate to the
RC32438 that access to the PCI bus has been granted.
PCIGNTN[1]: this signal takes on the alternate function of PCIEECS and is used
as a PCI Serial EEPROM chip select
PCIGNTN[3:2]: unused and driven high.
Note: When the GPIO register is programmed in the alternate function mode for
bits GPIO [26] and [28], these bits become PCIGNTN [4] and [5] respectively.
PCI Initiator Ready. Driven by the bus master to indicate that the current datum
can complete.
PCI Lock. This signal is asserted by an external bus master to indicate that an
exclusive operation is occurring.
PCI Parity. Even parity of the PCIAD[31:0] bus. Driven by the bus master during
address and write Data phases. Driven by the bus target during the read data
phase.
PCI Parity Error. If a parity error is detected, this signal is asserted by the
receiving bus agent 2 clocks after the data is received.
Table 1 Pin Description (Part 3 of 9)
6 of 59
Name/Description
May 25, 2004