79RC32K438-233BBI IDT, 79RC32K438-233BBI Datasheet
79RC32K438-233BBI
Specifications of 79RC32K438-233BBI
Related parts for 79RC32K438-233BBI
79RC32K438-233BBI Summary of contents
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... Supports up to 2GB of DDR SDRAM – 2 chip selects (each chip select supports 4 internal DDR banks) – Supports 16-bit or 32-bit data bus width using 8, 16, or 32-bit devices – Supports 64Mb, 128Mb, 256Mb, 512Mb, and 1Gb DDR SDRAM devices – Data bus multiplexing support allows interfacing to standard DDR DIMMs and SODIMMs – ...
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... Debug Support – Rev. 2.6 compliant EJTAG Interface Device Overview The RC32438 is a member of the IDT™ Interprise™ family of PCI integrated communications processors. It incorporates a high perfor- mance CPU core and a number of on-chip peripherals. The integrated processor is designed to transfer information from I/O modules to main memory with minimal CPU intervention using a highly sophisticated direct memory access (DMA) engine ...
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... IDT 79RC32438 card application the primary PCI controller in the system. The PCI interface can be operated synchronously or asynchronously to the other I/O interfaces on the RC32438 device. Ethernet Interface The RC32438 has two Ethernet Channels supporting 10Mbps and 100Mbps speeds to provide a standard media independent interface (MII) off-chip, allowing a wide range of external devices to be connected efficiently ...
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... O External Buffer Direction. Memory and peripheral bus external data bus buffer direction control. If the RC32438 memory and peripheral bus is connected to the A side of a transceiver, such as an IDT74FCT245, then this pin may be directly connected to the direction control (e.g., BDIR) pin of the transceiver. O Bus Grant. This signal is asserted by the RC32438 to indicate that the RC32438 has relinquished ownership of the memory and peripheral bus ...
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... IDT 79RC32438 Signal WAITACKN DDR Bus DDRADDR[13:0] DDRBA[1:0] DDRCASN DDRCKE DDRCKN[1:0] DDRCKP[1:0] DDRCSN[1:0] DDRDATA[31:0] DDRDM[7:0] DDRDQS[3:0] DDROEN[3:0] DDRRASN Type Name/Description I Wait or Transfer Acknowledge. When configured as wait, this signal is asserted during a memory and peripheral bus transaction to extend the bus cycle. When configured as a transfer acknowledge, this signal is asserted during a transaction to signal the completion of the transaction ...
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... IDT 79RC32438 Signal DDRVREF DDRWEN PCI Bus PCIAD[31:0] PCICBEN[3:0] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[3:0] PCIIRDYN PCILOCKN PCIPAR PCIPERRN Type Name/Description I DDR Voltage Reference. SSTL_2 DDR voltage reference generated by an external source. O DDR Write Enable. DDR write enable is asserted during DDR write transac- tions ...
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... IDT 79RC32438 Signal PCIREQN[3:0] PCIRSTN PCISERRN PCISTOPN PCITRDYN General Purpose Input/Output GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] Type Name/Description I/O PCI Bus Request. In PCI host mode with internal arbiter: These signals are inputs whose assertion indicates to the internal RC32438 arbiter that an agent desires ownership of the PCI bus. ...
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... IDT 79RC32438 Signal GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] GPIO[16] GPIO[17] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: U0RTSN Alternate function: UART channel 0 request to send output. I/O General Purpose I/O. ...
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... IDT 79RC32438 Signal GPIO[18] GPIO[19] GPIO[20] GPIO[21] GPIO[22] GPIO[23] GPIO[24] GPIO[25] GPIO[26] GPIO[27] GPIO[28] GPIO[29] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: DMAFINN0 Alternate function: External DMA channel 0 finished output. I/O General Purpose I/O. ...
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... IDT 79RC32438 Signal GPIO[30] GPIO[31] SPI Interface SCK SDI SDO Bus Interface SCL SDA Ethernet Interfaces MII0CL MII0CRS MII0RXCLK MII0RXD[3:0] MII0RXDV MII0RXER MII0TXCLK MII0TXD[3:0] MII0TXENP MII0TXER MII1CL Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCIMUINTN Alternate function: PCI Messaging unit interrupt output ...
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... IDT 79RC32438 Signal MII1CRS MII1RXCLK MII1RXD[3:0] MII1RXDV MII1RXER MII1TXCLK MII1TXD[3:0] MII1TXENP MII1TXER MIIMDC MIIMDIO JTAG / EJTAG EJTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS Type Name/Description I Ethernet 1 MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle. ...
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... IDT 79RC32438 Signal JTAG_TRST_N Debug CPU INST Pin Characteristics Note: Some input pads of the RC32438 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs (such as BRN) which, if left floating, could adversely affect the RC32438’s operation ...
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... IDT 79RC32438 Function Pin Name DDR Bus DDRADDR[13:0] DDRBA[1:0] DDRCASN DDRCKE DDRCKN[1:0] DDRCKP[1:0] DDRCSN[1:0] DDRDATA[31:0] DDRDM[7:0] DDRDQS[3:0] DDROEN[3:0] DDRRASN DDRVREF DDRWEN 3 PCI Bus Interface PCIAD[31:0] PCICBEN[3:0] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[3:0] PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN[3:0] PCIRSTN PCISERRN PCISTOPN PCITRDYN General Purpose ...
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... IDT 79RC32438 Function Pin Name Serial Interface SCK SDI SDO 2 I C-Bus Interface SCL SDA Ethernet Interfaces MII0CL MII0CRS MII0RXCLK MII0RXD[3:0] MII0RXDV MII0RXER MII0TXCLK MII0TXD[3:0] MII0TXENP MII0TXER MII1CL MII1CRS MII1RXCLK MII1RXD[3:0] MII1RXDV MII1RXER MII1TXCLK MII1TXD[3:0] MII1TXENP MII1TXER MIIMDC MIIMDIO EJTAG / ICE ...
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... External pull-up required in most system applications. Some applications may require additional pull-ups not identified in this table. 2. Schmidt Trigger Input (STI). 3. The PCI pins have internal pull-ups but they are too weak to guarantee system validity. Therefore, board pull-ups are mandatory where indicated. GPIO alternate function pins for PCI must also have board pull-ups. ...
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... MDATA[11:9] MDATA[12] MDATA[15:13] Name/Description Boot Device Width. This field specifies the width of the boot device (i.e., Device 0). 0x0 - 8-bit boot device width 0x1 - 16-bit boot device width Reset Mode. This bit specifies the length of time the RSTN signal is driven. 0x0 - Normal reset: RSTN driven for minimum of 4096 clock cycles 0x1 - reserved PCI Mode ...
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... IDT 79RC32438 Logic Diagram — RC32438 Miscellaneous Signals Ethernet EJTAG / JTAG Signals Debug Signals General Purpose I C-Bus Serial I/O CLK COLDRSTN RSTN EXTCLK MIIMDC MIIMDIO MII0CL MII0CRS MII0RXCLK 4 MII0RXD[3:0] MII0RXDV MII0RXER MII0TXCLK 4 MII0TXD[3:0] MII0TXENP MII0TXER MII1CL MII1CRS MII1RXCLK 4 MII1RXD[3:0] MII1RXDV MII1RXER ...
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... Input hold. Amount of time after the reference clock edge that the input must remain valid. Tpw Pulse width. Amount of time the input or output is active for asynchronous signals. Tslew Slew rate. The rise or fall rate for a signal to go from a high to low, or low to high. ...
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... IDT 79RC32438 System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 15 and 16. Parameter Symbol 1 PCLK Frequency Tper 2,3,4 ICLK Frequency Tper 5 CLK Frequency Tper_5a Thigh_5a, Tlow_5a Trise_5a, Tfall_5a Tjitter_5a 1. The CPU pipeline clock (PCLK) speed is selected during cold reset by the boot configuration vector (see Table 3). ...
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... Tdz_6d RSTN falling 2 Tzd_6d RSTN rising 1. The COLDRSTN minimum pulse width is the oscillator stabilization time (OSC) plus 0.5 ms with V 2. The values for this symbol were determined by calculation, not by testing. 3. RSTN is a bidirectional signal treated as an asynchronous input CLK ...
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... IDT 79RC32438 CLK COLDRSTN RSTN MDATA[15:0] Mem Control Signals EXTCLK 1. Warm reset caused by any of the conditions listed in the Warm Reset section of Chapter 3, Clocking and Initialization, in the RC32438 User Reference Manual. 2. The RC32438 tri-states the data bus, MDATA[15:0], and negates all memory control signals. ...
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... IDT 79RC32438 DDRCKPx DDRCKNx DDRCSNx DDRADDR[13:0] 1 NOP DDRCMD DDRCKE DDRBA[1:0] DDRDM[7:0] DDROEN[3:0] DDRDQSx (ideal) 2 DDRDATA[31:0] (ideal) DDRDQSx (min) 2 DDRDATA[31:0] DDRDQSx (max) 2 DDRDATA[31:0] 1 DDRCMD contains DDRRASN, DDRCASN and DDRWEN. 2 DDRDATA is either 32-bits or 16-bits wide depending on the DBW control bit in DDRC Register (see Chapter 7, DDR Controller, in the RC32438 User Reference Manual). ...
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... IDT 79RC32438 DDRCKPx DDRCKNx DDRCSNx DDRADDR[13:0] 1 NOP DDRCMD DDRCKE DDRBA[1:0] DDROEN[3:0] DDRDQSx DDRDM[7:0] DDRDQSx 2 DDRDATA[31:0] 1 DDRCMD contains DDRRASN, DDRCASN and DDRWEN. 2 DDRDATA is either 32-bits or 16-bits wide depending on the DBW control bit in DDRC Register (see Chapter 7, DDR Controller, in the RC32438 User Reference Manual). ...
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... IDT 79RC32438 Reference Signal Symbol Edge MDATA[15:0] Tsu_8c EXTCLK rising Thld_8c Tdo_8c 2 Tdz_8c 2 Tzd_8c 3 EXTCLK Tper_8d none BDIRN Tdo_8e EXTCLK rising 2 Tdz_8e 2 Tzd_8e BOEN Tdo_8f EXTCLK rising 2 Tdz_8f 2 Tzd_8f BRN Tsu_8g EXTCLK rising Thld_8g BGN Tdo_8h EXTCLK rising 4 WAITACKN Tsu_8h EXTCLK rising ...
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... The values for this symbol were determined by calculation, not by testing. 3. The frequency of EXTCLK is programmable. See the External Clock Divider description in Table 3 of this data sheet. 4. WAITACKN must meet the setup and hold times synchronous or the minimum pulse width asynchronous. EXTCLK MADDR[21:0] MADDR[25:22] ...
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... IDT 79RC32438 EXTCLK MADDR[21:0] MADDR[25:22] RWN CSN[5:0] 1111 BWEN[1:0] OEN MDATA[15:0] BDIRN BOEN WAITACKN CPU, INST Figure 9 Memory and Peripheral Bus AC Timing Waveform — Write Access EXTCLK DMADONENx MDATA[15:0] MADDR[25:0] DMAFINNx Tdo_8a Addr[21:0] Tdo_8b Addr[25:22] Tdo_8j Tdo_8i Tdo_8l Byte Enables Tdo_8c ...
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... IDT 79RC32438 EXTCLK DMAREQN ICLK CSN Tpw_8n is the minimum amount of time before DMAREQN is recognized as asserted or deasserted. Reference Signal Symbol Edge 1 Ethernet MIIMDC Tper_9a None Thigh_9a, Tlow_9a MIIMDIO Tsu_9b MIIMDC rising Thld_9b 2 Tdo_9b MIIxRXCLK, Tper_9c None 3 MIIxTXCLK Thigh_9c, Tlow_9c Trise_9c, Tfall_9c MIIxRXCLK, ...
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... IDT 79RC32438 3. The ethernet clock (MIIxRXCLK and MIIxTXCLK) frequency must be equal to or less than 1/2 ICLK (MIIxRXCLK and MIIxTXCLK <= 1/2(ICLK)). MIIxRXDV, MIIxRXD[3:0], MIIxRXER MIIxTXEN, MIIxTXD[3:0], MIIxTXER Tper_9d MIIxRXCLK Thld_9e Tsu_9e Tper_9d MIIxTXCLK Tdo_9f Tper_9a MIIxMDC Tdo_9b MIIxMDIO (output) Tsu_9b MIIxMDIO (input) Figure 12 Ethernet AC Timing Waveform ...
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... IDT 79RC32438 Reference Signal Symbol Edge 1 PCI 2 PCICLK Tper_10a none Thigh_10a, Tlow_10a Tslew_10a PCIAD[31:0], Tsu_10b PCICLK rising PCIBEN[3:0], Thld_10b PCIDEVSELN, PCIFRAMEN,PCIIR- Tdo_10b DYN, PCILOCKN, 3 Tdz_10b PCIPAR, PCI- PERRN, PCIS- 3 Tzd_10b TOPN, PCITRDY PCIGNTN[3:0], Tsu_10c PCICLK rising PCIREQN[3:0] Thld_10c Tdo_10c 4 3 PCIRSTN (output) ...
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... IDT 79RC32438 PCICLK Bussed output Point to point output Bussed input Point to point input COLDRSTN PCIRSTN (output) RSTN Note: During and after cold reset, PCIRSTN is tri-stated and requires a pull-down to reach a low state. After the PCI interface is enabled in host mode, PCIRSTN will be driven either high or low depending on the reset state of the 79RC32438 ...
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... IDT 79RC32438 Reference Signal Symbol SCL Frequency none Thigh_12a, Tlow_12a Trise_12a Tfall_12a SDA Tsu_12b SCL rising Thld_12b Trise_12b Tfall_12b Start or repeated start Tsu_12c SDA falling condition Thld_12c Stop condition Tsu_12d SDA rising Bus free time between Tdelay_12e a stop and start condi- ...
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... GPIO[31:0] Tpw_13b None 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. GPIO (synchronous output) GPIO (synchronous input) GPIO (asynchronous input) ...
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... In SPI mode, the SCK period and sampling edge are programmable. In PCI mode, the SCK period is fixed and the sampling edge is rising. 2. PCIEECS is the PCI serial EEPROM chip select alternate function of PCIGNTN[1 Bit I/O mode, SCK, SDI, and SDO must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tper_15a SCK Tdo_15d ...
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... IDT 79RC32438 Tper_15a SCK SDI MSB SDO MSB Control bits CPOL = 0, CPHA = 0 in the SPI Control Register, SPC. Figure 19 SPI AC Timing Waveform — Clock Polarity 0, Clock Phase 0 Tper_15a SCK SDI SDO Control bits CPOL = 0, CPHA = 1 in the SPI Control Register, SPC. ...
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... IDT 79RC32438 Reference Signal Symbol Edge EJTAG and JTAG JTAG_TCK Tper_16a none Thigh_16a, Tlow_16a 1 JTAG_TMS , Tsu_16b JTAG_TCK JTAG_TDI rising Thld_16b JTAG_TDO Tdo_16c JTAG_TCK falling 2 Tdz_16c 2 JTAG_TRST_N Tpw_16d none 1 EJTAG_TMS Tsu_16e JTAG_TCK rising Thld_6e VSENSE Trise_16f none 1. The JTAG specification, IEEE 1149.1, recommends that both JTAG_TMS and EJTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from ...
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... IDT 79RC32438 JTAG_TCK JTAG_TDI JTAG_TMS EJTAG_TMS JTAG_TDO JTAG_TRST_N The IEEE 1149.1 specification requires that the JTAG and EJTAG TAP controllers be reset at power-up whether or not the interfaces are used for a boundary scan or a probe. Reset can occur through a pull-down resistor on JTAG_TRST_N if the probe is not connected. However, on-chip pull-up resistors are implemented on the RC32438 due to an IEEE 1149 ...
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... IDT 79RC32438 Using the EJTAG Probe In Figure 23, the pull-up resistors for JTAG_TDO and RST*, the pull-down resistor for JTAG_TRST_N, and the series resistor for JTAG_TDO must be adjusted to the specific design. However, the recommended pull-up/down resistor is 1.0 kΩ because a low value reduces crosstalk on the cable to the connector, allowing higher JTAG_TCK frequencies. A typical value for the series resistor is 33 Ω ...
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... All speeds 1 1 200MHz, 233MHz 266MHz, 300MHz 200MHz, 233MHz 266MHz, 300MHz All speeds 0.5(VccSI/O) DDRVREF - 0.04 Table 15 RC32438 Operating Voltages Grade Commercial Industrial Table 16 RC32438 Operating Temperatures on the IDT web site (www.idt.com RC32438 V PLL cc V PLL cc V PLL ss V PLL ss Typical ...
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... IDT 79RC32438 Power-on Sequence Three power-on sequences are given below. Sequence #1 is recommended because it will prevent I/O conflicts and will also allow the input signals to propagate when the I/O powers are brought up. Note: The ESD diodes may be damaged if one of the voltages is applied and one of the other voltages ground level. ...
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... IDT 79RC32438 Power Consumption Parameter 200MHz Typ. I I/O 130 cc I SI/O 100 cc I Core, Normal 460 cc I PLL mode cc Power Normal 1.2 Dissipation mode DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 15. Note: See Table 2, Pin Characteristics, for a complete I/O listing. Para- ...
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... IDT 79RC32438 Para- I/O Type meter PCI I (AC) OH Switching I (AC) Switch- OL ing Capacitance C IN Inputs Leakage I/O / LEAK W O Pull-ups/downs with I/O LEAK Pull-ups/downs AC Test Conditions RC32438 Output Min. Typical Max. — -12(V I/O) cc — -17.1(V I OUT — — -32(V — +16(V I/O) cc — +26.7(V ) OUT — — ...
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... IDT 79RC32438 Absolute Maximum Ratings Symbol Core CC V PLL CC VinI/O VinSI Industrial T a Commercial Functional and tested operating conditions are given in Table 15. Absolute maximum ratings are stress ratings only, and func- tional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause perma- nent damage to the device ...
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... IDT 79RC32438 Package Pin-out — 416-PBGA Signal Pinout for RC32438 The following table lists the pin numbers, signal names, and number of alternate functions for the RC32438 device. Signal names ending with an “_N” or “N” are active when low. Pin Function ...
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... IDT 79RC32438 Pin Function Alt Pin B9 MDATA[11] G3 B10 MDATA[03] G4 B11 MDATA[08] G23 B12 MDATA[02] G24 B13 GPIO[23] 1 G25 B14 MADDR[20] G26 B15 GPIO[20 B16 MADDR[17] H2 B17 MADDR[14] H3 B18 MADDR[12] H4 B19 MADDR[09] H23 B20 MADDR[06] H24 B21 MADDR[03] H25 B22 MADDR[00] ...
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... IDT 79RC32438 Pin Function Alt Pin C20 MADDR[08] L26 C21 MADDR[04] M1 C22 MADDR[01] M2 C23 DDRDATA[00] M3 C24 DDRDATA[03] M4 C25 DDRDATA[08] M23 C26 DDRDATA[07] M24 D1 MII0RXD[03] M25 D2 MII0RXD[01] M26 D3 MII0RXD[02 I/O N23 I/O N24 I/O N25 cc D10 ...
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... IDT 79RC32438 RC32438 Ground Pins D10 D11 D12 D16 D17 D18 D19 G23 H4 H23 J4 J23 K10 K11 K12 K13 K14 K15 K16 K17 K23 L10 P13 L11 P14 L12 P15 L13 P16 L14 P17 L15 R3 L16 ...
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... IDT 79RC32438 RC32438 Alternate Signal Functions Pin GPIO Alternate A14 GPIO[22] MADDR[24] B13 GPIO[23] MADDR[25] B15 GPIO[20] MADDR[22] C16 GPIO[21] MADDR[23] N3 GPIO[01] U0SINP P1 GPIO[00] U0SOUT P3 GPIO[02] U0RIN T2 GPIO[03] U0DCDN V3 GPIO[05] U0DSRN W1 GPIO[04] U0DTRN RC32438 Signals Listed Alphabetically The following table lists the RC32438 pins in alphabetical order. ...
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... IDT 79RC32438 Signal Name DDRADDR[00] DDRADDR[01] DDRADDR[02] DDRADDR[03] DDRADDR[04] DDRADDR[05] DDRADDR[06] DDRADDR[07] DDRADDR[08] DDRADDR[09] DDRADDR[10] DDRADDR[11] DDRADDR[12] DDRADDR[13] DDRBA[00] DDRBA[01] DDRCASN DDRCKE DDRCKN[00] DDRCKN[01] DDRCKP[00] DDRCKP[01] DDRCSN[00] DDRCSN[01] DDRDATA[00] DDRDATA[01] DDRDATA[02] DDRDATA[03] DDRDATA[04] DDRDATA[05] DDRDATA[06] DDRDATA[07] DDRDATA[08] DDRDATA[09] DDRDATA[10] I/O Type Location ...
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... IDT 79RC32438 Signal Name DDRDATA[11] DDRDATA[12] DDRDATA[13] DDRDATA[14] DDRDATA[15] DDRDATA[16] DDRDATA[17] DDRDATA[18] DDRDATA[19] DDRDATA[20] DDRDATA[21] DDRDATA[22] DDRDATA[23] DDRDATA[24] DDRDATA[25] DDRDATA[26] DDRDATA[27] DDRDATA[28] DDRDATA[29] DDRDATA[30] DDRDATA[31] DDRDM[00] DDRDM[01] DDRDM[02] DDRDM[03] DDRDM[04] DDRDM[05] DDRDM[06] DDRDM[07] DDRDQS[00] DDRDQS[01] DDRDQS[02] DDRDQS[03] DDROEN[00] DDROEN[01] I/O Type Location ...
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... IDT 79RC32438 Signal Name DDROEN[02] DDROEN[03] DDRRASN DDRVREF DDRWEN EJTAG_TMS EXTCLK GPIO[00] GPIO[01] GPIO[02] GPIO[03] GPIO[04] GPIO[05] GPIO[06] GPIO[07] GPIO[08] GPIO[09] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] GPIO[16] GPIO[17] GPIO[18] GPIO[19] GPIO[20] GPIO[21] GPIO[22] GPIO[23] GPIO[24] GPIO[25] GPIO[26] GPIO[27] I/O Type Location ...
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... IDT 79RC32438 Signal Name GPIO[28] GPIO[29] GPIO[30] GPIO[31] INST JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MADDR[00] MADDR[01] MADDR[02] MADDR[03] MADDR[04] MADDR[05] MADDR[06] MADDR[07] MADDR[08] MADDR[09] MADDR[10] MADDR[11] MADDR[12] MADDR[13] MADDR[14] MADDR[15] MADDR[16] MADDR[17] MADDR[18] MADDR[19] MADDR[20] MADDR[21] MDATA[00] MDATA[01] I/O Type Location I/O AF5 ...
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... IDT 79RC32438 Signal Name MDATA[02] MDATA[03] MDATA[04] MDATA[05] MDATA[06] MDATA[07] MDATA[08] MDATA[09] MDATA[10] MDATA[11] MDATA[12] MDATA[13] MDATA[14] MDATA[15] MII0CL MII0CRS MII0RXCLK MII0RXD[00] MII0RXD[01] MII0RXD[02] MII0RXD[03] MII0RXDV MII0RXER MII0TXCLK MII0TXD[00] MII0TXD[01] MII0TXD[02] MII0TXD[03] MII0TXENP MII0TXER MII1CL MII1CRS MII1RXCLK MII1RXD[00] MII1RXD[01] I/O Type Location ...
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... IDT 79RC32438 Signal Name MII1RXD[02] MII1RXD[03] MII1RXDV MII1RXER MII1TXCLK MII1TXD[00] MII1TXD[01] MII1TXD[02] MII1TXD[03] MII1TXENP MII1TXER MIIMDC MIIMDIO OEN PCIAD[00] PCIAD[01] PCIAD[02] PCIAD[03] PCIAD[04] PCIAD[05] PCIAD[06] PCIAD[07] PCIAD[08] PCIAD[09] PCIAD[10] PCIAD[11] PCIAD[12] PCIAD[13] PCIAD[14] PCIAD[15] PCIAD[16] PCIAD[17] PCIAD[18] PCIAD[19] PCIAD[20] I/O Type Location ...
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... IDT 79RC32438 Signal Name PCIAD[21] PCIAD[22] PCIAD[23] PCIAD[24] PCIAD[25] PCIAD[26] PCIAD[27] PCIAD[28] PCIAD[29] PCIAD[30] PCIAD[31] PCICBEN[00] PCICBEN[01] PCICBEN[02] PCICBEN[03] PCICLK PCIDEVSELN PCIFRAMEN PCIGNTN[00] PCIGNTN[01] PCIGNTN[02] PCIGNTN[03] PCIIRDYN PCILOCKN PCIPAR PCIPERRN PCIREQN[00] PCIREQN[01] PCIREQN[02] PCIREQN[03] PCIRSTN PCISERRN PCISTOPN PCITRDYN RSTN RWN I/O Type ...
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... IDT 79RC32438 Signal Name SCK SCL SDA SDI SDO Vcc CORE Vcc I/O, Vcc SI/O Vcc PLL Vss Vss PLL WAITACKN I/O Type Location I/O W2 I/O AF4 I/O AD4 I/O V2 I/O V1 D13, D14, D15, K4, L4, L23, M4, M23, N4, N23, P23, AC13, AC14, AC15 See Table 21 for a listing of power pins. ...
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... IDT 79RC32438 RC32438 Pinout — Top View VccPLL AA VssPLL VccPLL AB AC VssPLL Vss (Ground) Vcc SI/O (Power) Vcc I/O (Power) Vcc Core (Power ...
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... IDT 79RC32438 RC32438 Package Drawing — 416-pin BGA May 25, 2004 ...
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... IDT 79RC32438 RC32438 Package Drawing — Page Two May 25, 2004 ...
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... Ordering Information YY XXXX 79RCXX Product Operating Device Type Type Voltage Valid Combinations 79RC32K438 -200BB, 233BB, 266BB, 300BB 79RC32K438 -200BBI, 233BBI CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 999 A Temp range/ Package Speed Process 416-pin BGA package, Commercial Temperature ...