79RC32K438-233BBI IDT, 79RC32K438-233BBI Datasheet - Page 15

• Manufacturer Part Number: 79RC32K438-233BBI
• Description: Processors - Application Specialized
• Manufacturer: IDT

Specifications of 79RC32K438-233BBI

• Part # Aliases: IDT79RC32K438-233BBI

Boot Configuration Vector
once the cold reset completes.
tion vector read in by the RC32438 during a cold reset may be determined by reading the Boot Configuration Vector (BCV) Register.
IDT 79RC32438
The boot configuration vector is read by the RC32438 during a cold reset. The vector defines essential RC32438 parameters that are required
The encoding of the boot configuration vector is described in Table 3, and the vector input is illustrated in Figure 4. The value of the boot configura-
Miscellaneous
1.
2.
3.
4.
5.
External pull-up required in most system applications. Some applications may require additional pull-ups not identified in this table.
Schmidt Trigger Input (STI).
The PCI pins have internal pull-ups but they are too weak to guarantee system validity. Therefore, board pull-ups are mandatory
PCIMUINTN is an alternate function of GPIO[30]. When configured as an alternate function, this pin is tri-stated when not asserted
Use a 2.2K pull-up resistor for I2C pins.
Function
where indicated. GPIO alternate function pins for PCI must also have board pull-ups.
(i.e., it acts as an open collector output).
MDATA[3:0]
MDATA[5:4]
MDATA[6]
Signal
CLK
EXTCLK
COLDRSTN
RSTN
Pin Name
CPU Pipeline Clock Multiplier. This field specifies the value by which the PLL multi-
plies the master clock input (CLK) to obtain the processor clock frequency (PCLK). For
master clock input frequency constraints, refer to Table 3.1 in the RC32438 User Man-
ual.
0x0 - PLL Bypass
0x1 - Multiply by 3
0x2 - Multiply by 4
0x3 - Multiply by 6
0x4 - Multiply by 8
0x5 - reserved
0x6 - reserved
0x7 - reserved
0x8 - reserved
0xD - reserved
0xE - reserved
0xF - reserved
External Clock Divider. This field specifies the value by which the IPBus clock
(ICLK), which is always 1/2 PCLK, is divided in order to generate the external clock
output on the EXTCLK pin.
0x0 - Divide by 1
0x1 - Divide by 2
0x2 - Divide by 4
0x3 - reserved
Endian. This bit specifies the endianness.
0x0 - little endian
0x1 - big endian
Table 3 Boot Configuration Encoding (Part 1 of 2)
Table 2 Pin Characteristics (Part 4 of 4)
Type
I/O
O
I
I
15 of 59
Buffer
LVTTL
LVTTL
LVTTL
LVTTL
Name/Description
Low Drive / STI
I/O Type
High Drive
STI
STI
Resistor
Internal
pull-up
pull-up on board
Notes
1
May 25, 2004