79RC32K438-233BBI IDT, 79RC32K438-233BBI Datasheet - Page 19

• Manufacturer Part Number: 79RC32K438-233BBI
• Description: Processors - Application Specialized
• Manufacturer: IDT

Specifications of 79RC32K438-233BBI

• Part # Aliases: IDT79RC32K438-233BBI

System Clock Parameters
IDT 79RC32438
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 15 and 16.
PCLK
ICLK
CLK
1.
2.
3.
4.
5.
The CPU pipeline clock (PCLK) speed is selected during cold reset by the boot configuration vector (see Table 3).
ICLK is the internal IPBus clock. It is always equal to PCLK divided by 2. This clock cannot be sampled externally.
The ethernet clock (MIIxRXCLK and MIIxTXCLK) frequency must be equal to or less than 1/2 ICLK (MIIxRXCLK and MIIxTXCLK <= 1/2(ICLK)).
PCICLK must be equal to or less than two times ICLK (PCICLK <= 2(ICLK)) with a maximum PCICLK of 66MHz.
The input clock (CLK) is input from the external oscillator to the internal PLL.
5
Parameter
2,3,4
1
CLK
Symbol
Frequency
Frequency
Frequency
Thigh_5a,
Trise_5a,
Tjitter_5a
Tlow_5a
Tper_5a
Tfall_5a
Tper
Tper
Tjitter_5a
Reference
Edge
none
none
none
Tper_5a
Figure 3 Clock Parameters Waveform
Min
10.0
15.0
200MHz
200
100
5.0
25
40
—
—
Table 5 Clock Parameters
Tjitter_5a
Max
10.0
66.6
40.0
200
100
5.0
3.0
0.1
19 of 59
60
Min
10.0
12.9
233MHz
200
100
4.2
25
40
—
—
Max
116.5
Thigh_5a
77.6
40.0
233
5.0
8.5
3.0
0.1
60
Min
10.0
11.2
266MHz
200
100
3.8
25
40
—
—
Tlow_5a
Trise_5a
Max
88.6
40.0
266
133
5.0
7.5
3.0
0.1
60
Min
300MHz
200
100
3.3
6.7
25
10
40
—
—
Tfall_5a
Max
10.0
300
150
100
5.0
3.0
0.1
40
60
Tper_5a
Units
MHz
MHz
MHz
% of
ns
ns
ns
ns
ns
See Figure 3.
Reference
Diagram
May 25, 2004
Timing