79RC32K438-233BBI IDT, 79RC32K438-233BBI Datasheet - Page 25

• Manufacturer Part Number: 79RC32K438-233BBI
• Description: Processors - Application Specialized
• Manufacturer: IDT

Specifications of 79RC32K438-233BBI

• Part # Aliases: IDT79RC32K438-233BBI

DMAREQN[1:0]
DMADONEN[1:0]
DMAFINN[1:0]
CPU, INST
1.
2.
3.
4.
IDT 79RC32438
The RC32438 provides bus turnaround cycles to prevent bus contention when going from a read to write, write to read, and during external bus ownership. For example, there are
The values for this symbol were determined by calculation, not by testing.
The frequency of EXTCLK is programmable. See the External Clock Divider description in Table 3 of this data sheet.
WAITACKN must meet the setup and hold times if it is synchronous or the minimum pulse width if it is asynchronous.
no cycles where an external device and the RC32438 are both driving. See Chapter 6, Device Controller, in the RC32438 User Reference Manual.
Signal
MADDR[25:22]
MADDR[21:0]
MDATA[15:0]
WAITACKN
BWEN[1:0]
CSN[5:0]
EXTCLK
BDIRN
BOEN
CPU,
RWN
INST
OEN
Symbol
Tpw_8n
Thld_8o
Tdo_8m
Tdo_8p
Tsu_8o
Tdz_8c
2
Reference
None
EXTCLK rising
EXTCLK rising
EXTCLK rising
Table 8 Memory and Peripheral Bus AC Timing Characteristics (Part 3 of 3)
Figure 8 Memory and Peripheral Bus AC Timing Waveform — Read Access
Tdo_8e
Edge
Tdo_8b
Tdo_8a
2(ICLK)
200MHz
Min
6.0
1.0
2.0
1.5
Tdo_8k
Tdo_8f
Max
10.0
6.0
—
—
—
2(ICLK)
233MHz
Min
Tdo_8m
6.0
1.0
1.5
2.0
Tdo_8i
25 of 59
RC32438
samples
read data
Max
10.0
6.0
—
—
Addr[21:0]
Tper_8d
Addr[25:22]
2(ICLK)
266MHz
Min
6.0
1.0
1.5
2.0
1111
Max
10.0
Data
6.0
—
—
—
Tsu_8c
Thld_8c
2(ICLK)
Tdo_8k
300MHz
Min
6.0
1.0
1.5
2.0
Tdo_8i
Tdo_8m
Max
10.0
6.0
—
—
—
Tdo_8f
Unit
ns
ns
ns
ns
ns
Conditions
Tdo_8e
Tzd_8c
Thigh_8d
May 25, 2004
See Figures 10
and 11.
See Figures 8
and 9.
Reference
Tlow_8d
Diagram
Timing