79RC32K438-233BBI IDT, 79RC32K438-233BBI Datasheet - Page 37

• Manufacturer Part Number: 79RC32K438-233BBI
• Description: Processors - Application Specialized
• Manufacturer: IDT

Specifications of 79RC32K438-233BBI

• Part # Aliases: IDT79RC32K438-233BBI

Using the EJTAG Probe
be adjusted to the specific design. However, the recommended pull-up/down resistor is 1.0 kΩ because a low value reduces crosstalk on the cable to
the connector, allowing higher JTAG_TCK frequencies. A typical value for the series resistor is 33 Ω. Recommended resistor values have ± 5% toler-
ance.
JTAG_TDO output is tri-stated. This requirement allows reliable connection of the probe if it is hooked-up when the power is already on (hot plug). The
pull-up resistor value of around 47 kΩ should be sufficient. Optional diodes to protect against overshoot and undershoot voltage can be added on the
signals of the chip with EJTAG.
actively pulled low only. The pull-up resistor is responsible for the high value when not driven by the probe of 25pF. The input on the target system
reset circuit must be able to accept the rise time when the pull-up resistor charges the capacitance to a high logical level. Vcc I/O must connect to a
voltage reference that drops rapidly to below 0.5V when the target system loses power, even with a capacitive load of 25pF. The probe can thus detect
the lost power condition.
Voltage Sense Signal Timing
target has powered-up. The probe is allowed to measure the T
stable indication in this case comes later than the time when target power is guaranteed to be stable. If JTAG_TRST_N is asserted by a pulse at
power-up, this reset must be completed after T
power-down, no power is indicated to the probe when Vcc I/O drops under the T
except for the probe RST*.
Phase-Locked Loop (PLL)
to create the processor clock (PCLK). Inherently, PLL circuits are only capable of generating clock frequencies within a limited range.
PLL Filters
considered as starting points for further experimentation within your specific application.
IDT 79RC32438
In Figure 23, the pull-up resistors for JTAG_TDO and RST*, the pull-down resistor for JTAG_TRST_N, and the series resistor for JTAG_TDO must
If a probe is used, the pull-up resistor on JTAG_TDO must ensure that the JTAG_TDO level is high when no probe is connected and the
If a probe is used, the RST* signal must have a pull-up resistor because it is controlled by an open-collector (OC) driver in the probe, and thus is
For additional information on EJTAG, refer to Chapter 20 of the RC32438 User Reference Manual.
The target system must ensure that T
The phase-locked loop (PLL) multiplies the external oscillator input (pin CLK) according to the parameter provided by the boot configuration vector
It is recommended that the system designer provide a filter network of passive components for the PLL analog and digital power supplies.
The
Because the optimum values for the filter components depend upon the application and the system noise environment, these values should be
PLL circuit power and PLL circuit ground should be isolated from power and ground with a filter circuit such as the one shown in Figure 25.
VSENSE
rise
is obeyed after the system reaches 0.5V (T
rise
T
. If JTAG_TRST_N is asserted by a pull-down resistor, the probe will control JTAG_TRST_N. At
active
Figure 24 Voltage Sense Signal Timing
rise
time from a higher value than T
37 of 59
T
rise_16f
active
value, which the probe uses to stop driving the input signals,
active
), so the probe can use this value to determine when the
active
(but lower than Vcc I/O minimum) because the
May 25, 2004