MCIMX6D4AVT08AC Freescale Semiconductor, MCIMX6D4AVT08AC Datasheet - Page 103

• Manufacturer Part Number: MCIMX6D4AVT08AC
• Description: Processors - Application Specialized i.MX6D AUTO
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6D4AVT08AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Operating Supply Voltage: 1.05 V to 1.5 V
• Memory Type: L1/L2 Cache, ROM, SRAM

4.11.10.6.3 TFT Panel Sync Pulse Timing Diagrams
Figure 69
the data. All the parameters shown in the figure are programmable. All controls are started by
corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of
the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals.
Freescale Semiconductor
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IPP_DISP_CLK
IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is
selected). In active mode, IPP_DISP_CLK runs continuously.
HSYNC causes the panel to start a new line. (Usually IPUx_DIx_PIN02 is used as HSYNC.)
VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
(Usually IPUx_DIx_PIN03 is used as VSYNC.)
DRDY acts like an output enable signal to the CRT display. This output enables the data to be
shifted onto the display. When disabled, the data is invalid and the trace is off.
(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)
IPP_DATA
depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
VSYNC
HSYNC
HSYNC
DRDY
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
Figure 68. Interface Timing Diagram for TFT (Active Matrix) Panels
LINE 1
1
LINE 2
2
LINE 3
3
LINE 4
LINE n-1
m–1
Electrical Characteristics
LINE n
m
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