MCIMX6D4AVT08AC Freescale Semiconductor, MCIMX6D4AVT08AC Datasheet - Page 78

• Manufacturer Part Number: MCIMX6D4AVT08AC
• Description: Processors - Application Specialized i.MX6D AUTO
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6D4AVT08AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Operating Supply Voltage: 1.05 V to 1.5 V
• Memory Type: L1/L2 Cache, ROM, SRAM

Electrical Characteristics
1
2
3
4
5
6
78
81
82
83
84
86
89
90
91
95
96
97
ID
87
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are the same clock)
bl = bit length
wl = word length
wr = word length relative
ESAI_TX_CLK(ESAI_TX_CLK pin) = transmit clock
ESAI_RX_CLK(ESAI_RX_CLK pin) = receive clock
ESAI_TX_FS(ESAI_TX_FS pin) = transmit frame sync
ESAI_RX_FS(ESAI_RX_FS pin) = receive frame sync
ESAI_TX_HF_CLK(ESAI_TX_HF_CLK pin) = transmit high frequency clock
ESAI_RX_HF_CLK(ESAI_RX_HF_CLK pin) = receive high frequency clock
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
Periodically sampled and not 100% tested.
ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) low
ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) high
ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) low
ESAI_TX_CLK rising edge to data out enable from high
impedance
ESAI_TX_CLK rising edge to data out valid
ESAI_TX_CLK rising edge to data out high impedance
ESAI_TX_FS input (bl, wr) setup time before
ESAI_TX_CLK falling edge
ESAI_TX_FS input (wl) setup time before ESAI_TX_CLK
falling edge
ESAI_TX_FS input hold time after ESAI_TX_CLK falling
edge
ESAI_RX_HF_CLK/ESAI_TX_HF_CLK clock cycle
ESAI_TX_HF_CLK input rising edge to ESAI_TX_CLK
output
ESAI_RX_HF_CLK input rising edge to ESAI_RX_CLK
output
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
Table 54. Enhanced Serial Audio Interface (ESAI) Timing (continued)
Parameter
5
1,2
67
5
Symbol
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Expression
2 x T
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C
2
18.0
18.0
Min
2.0
2.0
4.0
5.0
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
22.0
12.0
19.0
20.0
10.0
22.0
17.0
19.0
13.0
21.0
16.0
18.0
18.0
Freescale Semiconductor
9.0
—
—
—
—
—
—
—
Condition
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
—
—
—
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns