IS61WV25616BLL-10TL ISSI, Integrated Silicon Solution Inc, IS61WV25616BLL-10TL Datasheet - Page 15

• Manufacturer Part Number: IS61WV25616BLL-10TL
• Description: IC SRAM 4MBIT 10NS 44TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61WV25616BLL-10TL

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 4M (256K x 16)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TSOP II
• Density: 4Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 18b
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 35mA
• Operating Supply Voltage (min): 2.4V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1105; IS61WV25616BLL-10TL

IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
07/15/2010
AC WAVEFORMS
WRITE CYCLE NO. 3
WRITE CYCLE NO. 4
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
states to initiate a Write, but any can be deasserted to terminate the Write. The
rising or falling edge of the signal that terminates the Write.
ADDRESS
ADDRESS
UB, LB
UB, LB
D
D
OUT
OUT
WE
D
WE
OE
D
CE
OE
CE
IN
IN
LOW
LOW
LOW
DATA UNDEFINED
(WE Controlled. OE is LOW During Write Cycle)
(LB, UB Controlled, Back-to-Back Write)
t
DATA UNDEFINED
SA
t
HZWE
ADDRESS 1
t
SD
t
t
SA
WORD 1
WC
t
PBW
HIGH-Z
DATA
VALID
t
t
AW
HZWE
IN
VALID ADDRESS
t
t
PWE2
t
WC
t
PBW
t
HD
HA
t
HIGH-Z
SA
ADDRESS 2
t
t
SD
DATA
t
SD
WC
(1,3)
WORD 2
t
PBW
IN
DATA
VALID
VALID
t
SA
(1)
IN
,
t
t
HD
HA
t
LZWE
t
,
LZWE
t
t
SD
t
HA
t
HD
, and
HA
t
HD
UB_CEWR3.eps
UB_CEWR4.eps
timing is referenced to the
15
1
2
3
4
5
6
7
8
9
10
11
12