IS43R16160B-6TL ISSI, Integrated Silicon Solution Inc, IS43R16160B-6TL Datasheet - Page 27

IC DDR SDRAM 256MBIT 66TSOP

IS43R16160B-6TL

Manufacturer Part Number
IS43R16160B-6TL
Description
IC DDR SDRAM 256MBIT 66TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS43R16160B-6TL

Package / Case
66-TSOPII
Memory Size
256M (16Mx16)
Format - Memory
RAM
Memory Type
DDR SDRAM
Speed
166MHz
Interface
Parallel
Voltage - Supply
2.5 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Data Bus Width
16 bit
Maximum Clock Frequency
167 MHz
Access Time
0.7 ns
Supply Voltage (max)
2.7 V
Supply Voltage (min)
2.3 V
Maximum Operating Current
250 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1086
IS43R16160B-6TL

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Part Number
Manufacturer
Quantity
Price
Part Number:
IS43R16160B-6TL
Manufacturer:
ISSI
Quantity:
8 000
Part Number:
IS43R16160B-6TL
Manufacturer:
ISSI
Quantity:
20 000
Part Number:
IS43R16160B-6TLI
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TEMIC
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Part Number:
IS43R16160B-6TLI
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Quantity:
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IS43R83200B
IS43R16160B, IC43R16160B
Integrated Silicon Solution, Inc.
Rev. B
DDR SDRAM (Rev.1.1)
10/31/08
WRITE
the WRITE command with data strobe input, following (BL-1) data are written into RAM, when
the Burst Length is BL. The start address is specified by A0-9(x8)/A0-8(x16), and the address
sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any
active bank, so the row precharge time (tRP) can be hidden behind continuous input data by
interleaving the multiple banks. From the last data to the PRE command, the write recovery time
(tWRP) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge is complete. The next ACT command can be issued after tDAL from the last input data
cycle.
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from
Command
A0-9,11,12
BA0,1
/CLK
DQS
CLK
A10
DQ
Preliminary
Preliminary
ACT
Xa
Xa
Xa
00
D
tRCD
WRITE
Ya
00
Multi Bank Interleaving WRITE (BL=8)
0
Da0
ACT
Xb
Xb
10
Da1
Da2
Da3
D
tRCD
256M Double Data Rate Synchronous DRAM
Da4
Da5
WRITE
Da6
10
Yb
0
Da7
Db0
Db1
Zentel Electronics Corporation
Db2
PRE
00
0
Db3
A3S56D30/40ETP
Db4
Db5
Db6
Db7
PRE
10
0
27

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