IS42S16800E-7TL ISSI, Integrated Silicon Solution Inc, IS42S16800E-7TL Datasheet

Page 1

... OVERVIEW ISSI 's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized as follows. IS42S81600E Banks 54-pin TSOPII KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 APRIL 2011 IS42S16800E 2M x16 x4 Banks 54-pin TSOPII 54-ball TF-BGA - -75E Unit — 7.5 ns ...

Page 2

... IS42S81600E, IS42S16800E DEVICE OVERVIEW The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V V and 3.3V V memory systems containing 134,217,728 ddq bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is orga- nized as 4,096 rows by 512 columns by 16 bits or 4,096 rows by 1,024 columns by 8 bits. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK ...

Page 3

... IS42S81600E, IS42S16800E PIN CONFIGURATIONS 54 pin TSOP - Type II for x8 PIN DESCRIPTIONS A0-A11 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ7 Data I/O CLK System Clock Input CKE Clock Enable Chip Select CS RAS Row Address Strobe Command CAS Column Address Strobe Command Integrated Silicon Solution, Inc. — www.issi.com Rev. D 03/16/2011 DQ0 2 53 DQ7 DQ1 ...

Page 4

... IS42S81600E, IS42S16800E PIN CONFIGURATIONS 54 pin TSOP - Type II for x16 PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command Column Address Strobe Command CAS DQ0 2 53 DQ15 DQ1 4 51 DQ14 DQ2 5 50 DQ13 DQ3 7 DQ12 ...

Page 5

... IS42S81600E, IS42S16800E PIN CONFIGURATION 54-ball TF-BGA for x16 (Top View) (8. 8.00 mm Body, 0.8 mm Ball Pitch) PACKAGE CODE PIN DESCRIPTIONS A0-A11 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable Chip Select CS Row Address Strobe Command RAS CAS Column Address Strobe Command Integrated Silicon Solution, Inc. — www.issi.com Rev ...

Page 6

... IS42S81600E, IS42S16800E PIN FUNCTIONS Symbol Type A0-A11 Input Pin BA0, BA1 Input Pin CAS Input Pin CKE Input Pin CLK Input Pin Input Pin CS DQML, Input Pin DQMH DQM Input Pin DQ -DQ or Input/Output Input Pin RAS WE Input Pin V P ower Supply Pin ddq V P ower Supply Pin ower Supply Pin ssq V P ower Supply Pin ss 6 Function (In Detail) ...

Page 7

... IS42S81600E, IS42S16800E GENERAL DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0- A9 (x8); A0-A8 (x16) provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. The row will remain open for subsequent accesses when AUTO PRECHARGE is not selected. DQ’s read data is subject to the logic level on the DQM inputs two clocks earlier. When a given DQM signal was registered HIGH, the corresponding DQ’ ...

Page 8

... IS42S81600E, IS42S16800E COMMAND TRUTH TABLE CKE Function n – 1 Device deselect (DESL operation (NOP) H Burst stop (BST) H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate (ACT) H Precharge select bank (PRE) H Precharge all banks (PALL) H CBR Auto-Refresh (REF) H Self-Refresh (SELF) H Mode register set (MRS) H Note: H Valid Data DQM TRUTH TABLE Function Data write / output enable Data mask / output disable ...

Page 9

... IS42S81600E, IS42S16800E CKE TRUTH TABLE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle (REF) Self refresh entry Idle (SELF) Power down entry Idle Self refresh exit Power down exit Note: H Valid Data Integrated Silicon Solution, Inc. — www.issi.com Rev. D 03/16/2011 CKE n – RAS CAS × × × × × ...

Page 10

... IS42S81600E, IS42S16800E FUNCTIONAL TRUTH TABLE Current State CS RAS CAS WE Idle Row Active Read Write Note: H Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Address Command X X DESL H X NOP L X BST H BA, CA, A10 READ/READA L A, CA, A10 WRIT/ WRITA H BA, RA ACT L BA, A10 PRE/PALL H X REF/SELF ...

Page 11

... IS42S81600E, IS42S16800E FUNCTIONAL TRUTH TABLE Continued: Current State CS RAS CAS WE Read with auto H × × Precharging Write with Auto H × × Precharge Precharging H × × Row Activating H × × Note: H Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Integrated Silicon Solution, Inc. — www.issi.com Rev. D 03/16/2011 Address Command × ...

Page 12

... IS42S81600E, IS42S16800E FUNCTIONAL TRUTH TABLE Continued: Current State CS RAS CAS WE Write Recovering H × × Write Recovering H × × with Auto Precharge Refresh H × × Mode Register H × × Accessing L L × Note: H Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Notes: 1. All entries assume that CKE is active (CKEn-1=CKEn=H both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states ...

Page 13

... IS42S81600E, IS42S16800E CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh (S.R.) INVALID, CLK ( would exit S.R. Self-Refresh Recovery Self-Refresh Recovery Illegal Illegal Maintain S.R. Self-Refresh Recovery Idle After t rc Idle After t rc Illegal Illegal Begin clock suspend next cycle Begin clock suspend next cycle Illegal Illegal Exit clock suspend next cycle Maintain clock suspend Power-Down (P.D.) INVALID, CLK ( would exit P.D. EXIT P.D. --> Idle (2) Maintain power down mode Both Banks Idle ...

Page 14

... IS42S81600E, IS42S16800E STATE DIAGRAM Mode Register Set Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON 14 SELF SELF exit MRS IDLE CKE CKE ACT CKE Row Active CKE BST BST Read Write Read Write Precharge Integrated Silicon Solution, Inc. — www.issi.com ...

Page 15

... IS42S81600E, IS42S16800E ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage dd max V Maximum Supply Voltage for Output Buffer ddq max V Input Voltage in V Output Voltage out P Allowable Power Dissipation d max I output Shorted Current cs T operating Temperature opr T Storage Temperature stg Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All voltages are referenced to Vss. ...

Page 16

... IS42S81600E, IS42S16800E DC ELECTRICAL CHARACTERISTICS 1 Symbol Parameter i Operating Current (1) dd1 i Precharge Standby Current dd2p (In Power-Down Mode) i Precharge Standby Current dd2ps with clock stop (In Power-Down Mode) i Precharge Standby Current (2) dd2n (In Non Power-Down Mode) I Precharge Standby Current dd2ns with clock stop (In Non Power-Down Mode) i Active Standby Current (2) dd3p (In Power-Down Mode) i Active Standby Current dd3ps with clock stop (In Power-Down Mode) i Active Standby Current (2) dd3n (In Non Power-Down Mode) I Active Standby Current dd3ns with clock stop (In Non Power-Down Mode) i Operating Current dd4 i Auto-Refresh Current dd5 i Self-Refresh Current ...

Page 17

... IS42S81600E, IS42S16800E AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time ck3 t ck2 t Access Time From CLK ac3 t ac2 t CLK HIGH Level Width ch t CLK LOW Level Width cl t Output Data Hold Time oh3 t oh2 t Output LOW Impedance Time lz t Output HIGH Impedance Time hz t Input Data Setup Time ( Input Data Hold Time ( Address Setup Time ( Address Hold Time ( CKE Setup Time (2) cks t CKE Hold Time (2) ckh t Command Setup Time (CS, RAS, CAS, WE, DQM) cms t Command Hold Time (CS, RAS, CAS, WE, DQM) cmh ...

Page 18

... IS42S81600E, IS42S16800E OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency (CAS Latency = 3) t CAS Latency cac t Active Command To Read/Write Command Delay Time rcd t RAS Latency ( rac rcd cac t Command Period (REF to REF / ACT to ACT Command Period (ACT to PRE) ras t Command Period (PRE to ACT Command Period (ACT[0] to ACT [1]) ...

Page 19

... IS42S81600E, IS42S16800E AC TEST CONDITIONS Input Load t CH 3.0V 1.4V CLK CMS CMH 3.0V INPUT 1. OUTPUT 1.4V AC TEST CONDITIONS Parameter AC Input Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level Integrated Silicon Solution, Inc. — www.issi.com Rev. D 03/16/2011 Output Load Output t AC 1.4V 1.4V 50Ω 50Ω Rating ...

Page 20

... IS42S81600E, IS42S16800E FUNCTIONAL DESCRIPTION The 128Mb SDRAMs are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits or 4,096 rows by 1,024 columns by 8 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence ...

Page 21

... IS42S81600E, IS42S16800E INITIALIzE AND LOAD MODE REGISTER CLK CKS CKH CKE CMS CMH CMS CMH COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS Power-up: V Precharge CC and CLK stable all banks T = 100µs Min. ...

Page 22

... IS42S81600E, IS42S16800E AUTO-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z Notes: 1. CAS latency = Auto NOP Refresh Integrated Silicon Solution, Inc. — www.issi.com ...

Page 23

... IS42S81600E, IS42S16800E SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all active banks refresh mode Integrated Silicon Solution, Inc. — www.issi.com Rev. D ...

Page 24

... IS42S81600E, IS42S16800E REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. MODE REGISTER DEFINITION BA1 BA0 A11 A10 A9 (1) Reserved Write Burst Mode ...

Page 25

... IS42S81600E, IS42S16800E BURST LENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected ...

Page 26

... IS42S81600E, IS42S16800E CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge The DQs will start driving as a result of the clock edge one cycle earlier ( 1), and provided that the relevant access times are met, the data will be valid by clock edge For example, assuming that the clock ...

Page 27

... IS42S81600E, IS42S16800E CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the t specification. Minimum t should be divided by rcd rcd the clock period and rounded up to the next whole number ...

Page 28

... IS42S81600E, IS42S16800E READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the fol- lowing illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge ...

Page 29

... IS42S81600E, IS42S16800E minus one. This is shown in the READ to PRECHARGE diagram for each possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until t is met. Note that part of the row precharge time is rp hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge ...

Page 30

... IS42S81600E, IS42S16800E RW1 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 2 RW2 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL NOP NOP NOP NOP n+1 D n+2 OUT OUT OUT NOP NOP NOP OUT CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com ...

Page 31

... IS42S81600E, IS42S16800E CONSECUTIVE READ BURSTS T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 03/16/2011 NOP NOP NOP READ BANK, COL n+1 D OUT OUT ...

Page 32

... IS42S81600E, IS42S16800E RANDOM READ ACCESSES T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - READ READ READ BANK, BANK, BANK, COL b COL m COL OUT OUT CAS Latency - READ READ READ NOP BANK, BANK, BANK, COL b ...

Page 33

... IS42S81600E, IS42S16800E READ BURST TERMINATION T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 03/16/2011 BURST NOP NOP NOP TERMINATE n+1 D OUT OUT T2 T3 ...

Page 34

... IS42S81600E, IS42S16800E ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1) CAS latency = 2, Burst Length = 4 2) x16: A9 and A11 = " ...

Page 35

... IS42S81600E, IS42S16800E READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN A10 ROW BA0, BA1 BANK BANK DQ t RCD Notes: 1) CAS latency = 2, Burst Length = Full Page 2) x16: A9 and A11 = "Don't Care" ...

Page 36

... IS42S81600E, IS42S16800E READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD Notes: 1) CAS latency = 2, Burst Length = 4 2) x16: A9 and A11 = "Don't Care" ...

Page 37

... IS42S81600E, IS42S16800E READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 03/16/2011 NOP NOP NOP PRECHARGE BANK (a or all n+1 ...

Page 38

... IS42S81600E, IS42S16800E WRITES WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE COMMAND CLK HIGH CKE CS RAS CAS WE A0-A9 COLUMN ADDRESS A11 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS Note "Don't Care" for x16. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled ...

Page 39

... IS42S81600E, IS42S16800E WRITE BURST COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYCLES COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. D 03/16/2011 CLK WRITE NOP NOP BANK, COL n CLK COMMAND WRITE NOP BANK, ADDRESS COL n DON'T CARE CLK WRITE WRITE WRITE BANK, ...

Page 40

... IS42S81600E, IS42S16800E WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WP1 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL NOP READ NOP BANK, COL b D n+1 IN CAS Latency - NOP NOP PRECHARGE BANK (a or all) t DPL D n Integrated Silicon Solution, Inc. — www.issi.com ...

Page 41

... IS42S81600E, IS42S16800E WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. D 03/16/2011 NOP NOP PRECHARGE BANK (a or all) t DPL D n CLK BURST WRITE TERMINATE COMMAND BANK, (ADDRESS) COL n ...

Page 42

... IS42S81600E, IS42S16800E WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) Burst Length = Full Page 2) x16: A9 and A11 = "Don't Care" x8: A11 = "Don't Care" ...

Page 43

... IS42S81600E, IS42S16800E WRITE - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) Burst Length = 4 2) x16: A9 and A11 = "Don't Care" x8: A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev ...

Page 44

... IS42S81600E, IS42S16800E ALTERNATING BANK WRITE ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP WRITE t CMS DQM/DQML DQMH A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BANK 0 BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1) Burst Length = 4 2) x16: A9 and A11 = " ...

Page 45

... IS42S81600E, IS42S16800E CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time Clock Suspend During WRITE Burst T0 CLK CKE INTERNAL CLOCK COMMAND NOP ADDRESS DQ Clock Suspend During READ Burst ...

Page 46

... IS42S81600E, IS42S16800E CLOCK SUSPEND MODE CLK CKS CKH CKS CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/DQML DQMH A0-A9, A11 COLUMN m ( A10 BA0, BA1 BANK DQ Notes: 1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled. 2) x16: A9 and A11 = "Don't Care" x8: A11 = "Don't Care" ...

Page 47

... IS42S81600E, IS42S16800E PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE rp command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged the idle state and must be activated prior to any READ or WRITE commands being issued to that bank ...

Page 48

... IS42S81600E, IS42S16800E POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/DQML DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles All banks idle, enter Precharge all active banks power-down mode ...

Page 49

... IS42S81600E, IS42S16800E BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ISSI ...

Page 50

... IS42S81600E, IS42S16800E WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank n will begin after t is met, where t begins when the READ to bank m is dpl registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. ...

Page 51

... IS42S81600E, IS42S16800E SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 1 2) x16: A9 and A11 = "Don't Care" ...

Page 52

... IS42S81600E, IS42S16800E READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 4 2) x16: A9 and A11 = "Don't Care" ...

Page 53

... IS42S81600E, IS42S16800E SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 1 2) x16: A9 and A11 = "Don't Care" ...

Page 54

... IS42S81600E, IS42S16800E READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH A0-A9, A11 ROW COLUMN A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 4 2) x16: A9 and A11 = " ...

Page 55

... IS42S81600E, IS42S16800E SINGLE WRITE WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM/DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 1 2) x16: A9 and A11 = "Don't Care" ...

Page 56

... IS42S81600E, IS42S16800E SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/DQML DQMH A0-A9, A11 ROW DISABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 1 2) x16: A9 and A11 = "Don't Care" ...

Page 57

... IS42S81600E, IS42S16800E WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/DQML DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 4 2) x16: A9 and A11 = "Don't Care" ...

Page 58

... IS42S81600E, IS42S16800E WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP WRITE t CMS DQM/DQML DQMH A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK RCD t RAS t RC Notes: 1) Burst Length = 4 2) x16: A9 and A11 = "Don't Care" ...

Page 59

... IS42S81600E-75ETLI 54-Pin TSOPII, Lead-free Frequency Speed (ns) Order Part No. 200 MHz 5 IS42S16800E-5TLI IS42S16800E-5BLI 166 MHz 6 IS42S16800E-6TLI IS42S16800E-6BLI 143 MHz 7 IS42S16800E-7TLI IS42S16800E-7BLI 133 MHz 7.5 IS42S16800E-75ETLI 54-Pin TSOPII, Lead-free IS42S16800E-75EBLI 54-ball BGA, Lead-free *Contact Product Marketing for Leaded parts support. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 03/16/2011 = 3.3V DD Package 54-Pin TSOPII, Lead-free 54-Pin TSOPII, Lead-free ...

Page 60

... IS42S81600E, IS42S16800E 60 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 03/16/2011 ...

Page 61

... IS42S81600E, IS42S16800E Integrated Silicon Solution, Inc. — www.issi.com Rev. D 03/16/2011 61 ...