MT46V128M4FN-6:D TR Micron Technology Inc, MT46V128M4FN-6:D TR Datasheet - Page 87
![IC DDR SDRAM 512MBIT 6NS 60FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT46V128M4FN-6:D TR
Manufacturer Part Number
MT46V128M4FN-6:D TR
Description
IC DDR SDRAM 512MBIT 6NS 60FBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT46V32M16P-5BF_TR.pdf
(91 pages)
Specifications of MT46V128M4FN-6:D TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
512M (128Mx4)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
60-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1012-2
MT46V128M4FN-6:D
MT46V128M4FN-6:F
MT46V128M4FN-6:D
MT46V128M4FN-6:F
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Figure 52:
AUTO REFRESH
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
Command
BA0, BA1
Address
DQS
CK#
CKE
A10
DQ
DM
CK
4
t IS
t IS
NOP
T0
Bank WRITE – with Auto Precharge
t IH
1
t IH
Notes:
t IS
t IS
Bank x
ACT
Row
Row
T1
t IH
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. Enable auto precharge.
4. DI n = data-out from column n; subsequent elements are provided in the programmed
5. See Figure 50 on page 85 for detailed DQ timing.
During auto refresh, the addressing is generated by the internal refresh controller. This
makes the address bits a “Don’t Care” during an AUTO REFRESH command. The DDR
SDRAM requires AUTO REFRESH cycles at an average interval of
To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM, meaning that the maximum abso-
lute interval between any AUTO REFRESH command and the next AUTO REFRESH
command is 9 ×
specifications exceed the JEDEC requirement by one clock. This maximum absolute
interval is to allow future support for DLL updates, internal to the DDR SDRAM, to be
restricted to AUTO REFRESH cycles, without allowing excessive drift in
updates.
t IH
times.
order.
t CK
t RCD
t RAS
NOP
T2
1
t CH
t
REFI(=
t CL
t IS
Bank x
3
WRITE
Col n
T3
t IH
t DQSS (NOM)
2
t
REFC). JEDEC specifications only support 8 ×
t WPRES t WPRE
t DS
87
NOP
T4
DI
b
1
t DH
T4n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DQSL
NOP
T5
512Mb: x4, x8, x16 DDR SDRAM
t DQSH
1
T5n
t WPST
NOP
T6
1
Transitioning Data
©2000 Micron Technology, Inc. All rights reserved.
t
REFI (MAX).
t WR
NOP
T7
1
t
t
REFI; Micron
AC between
Operations
Don’t Care
NOP
T8
1
t RP
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