C8051F704-GQR Silicon Labs, C8051F704-GQR Datasheet - Page 236
![no-image](/images/no-image-200.jpg)
C8051F704-GQR
Manufacturer Part Number
C8051F704-GQR
Description
8-bit Microcontrollers - MCU 15kB 32B EEPROM ADC Cap Sense
Manufacturer
Silicon Labs
Datasheet
1.C8051F709-GQR.pdf
(306 pages)
Specifications of C8051F704-GQR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F704-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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- Download datasheet (2Mb)
C8051F70x/71x
236
1100
1000 1
1110
Values Read
Table 30.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0)
0
0
0
0 X
0
0
0 X
0
1
A master START was gener-
ated.
A master data or address byte
was transmitted; NACK
received.
A master data or address byte
was transmitted; ACK
received.
A master data byte was
received; ACK requested.
Current SMbus State
Rev. 1.0
Load slave address + R/W into
SMB0DAT.
Set STA to restart transfer.
Abort transfer.
Load next data byte into
SMB0DAT.
End transfer with STOP.
End transfer with STOP and start
another transfer.
Send repeated START.
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
Send NACK to indicate last byte,
and send STOP.
Send NACK to indicate last byte,
and send STOP followed by
START.
Send ACK followed by repeated
START.
Send NACK to indicate last byte,
and send repeated START.
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
Typical Response Options
Values to
0
1
0
0
0
1
1
0
0
0
1
1
1
0
0
Write
0 X 1100
0 X
1 X
0 X 1100
1 X
1 X
0 X
0 X 1000
0 1
1 0
1 0
0 1
0 0
0 1
0 0
1000
1100
1100
1110
1110
1110
1110
1110
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