C8051F704-GQR Silicon Labs, C8051F704-GQR Datasheet - Page 249
![no-image](/images/no-image-200.jpg)
C8051F704-GQR
Manufacturer Part Number
C8051F704-GQR
Description
8-bit Microcontrollers - MCU 15kB 32B EEPROM ADC Cap Sense
Manufacturer
Silicon Labs
Datasheet
1.C8051F709-GQR.pdf
(306 pages)
Specifications of C8051F704-GQR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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SFR Definition 31.2. SPI0CN: SPI0 Control
SFR Address = 0xF8; SFR Page = All Pages; Bit-Addressable
Name
Reset
Bit
3:2
Type
7
6
5
4
1
0
Bit
NSSMD[1:0]
RXOVRN
TXBMT
WCOL
SPIEN
MODF
Name
SPIF
SPIF
R/W
7
0
SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If SPI interrupts
are enabled, an interrupt will be generated. This bit is not automatically cleared by
hardware, and must be cleared by software.
Write Collision Flag.
This bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When
this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be
written. If SPI interrupts are enabled, an interrupt will be generated. This bit is not
automatically cleared by hardware, and must be cleared by software.
Mode Fault Flag.
This bit is set to logic 1 by hardware when a master mode collision is detected
(NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). If SPI interrupts are enabled, an
interrupt will be generated. This bit is not automatically cleared by hardware, and
must be cleared by software.
Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware when the receive buffer still holds unread data
from a previous transfer and the last bit of the current transfer is shifted into the
SPI0 shift register. If SPI interrupts are enabled, an interrupt will be generated. This
bit is not automatically cleared by hardware, and must be cleared by software.
Slave Select Mode.
Selects between the following NSS operation modes:
(See Section 31.2 and Section 31.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
WCOL
R/W
6
0
MODF
R/W
5
0
RXOVRN
R/W
Rev. 1.0
4
0
Function
3
0
NSSMD[1:0]
R/W
C8051F70x/71x
2
1
TXBMT
R
1
1
SPIEN
R/W
0
0
249
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