C8051F589-IMR Silicon Labs, C8051F589-IMR Datasheet - Page 333

• Manufacturer Part Number: C8051F589-IMR
• Description: 8-bit Microcontrollers - MCU 50MIPS 128kB 8kB SPI
• Manufacturer: Silicon Labs

Specifications of C8051F589-IMR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

29.2. PCA1 Interrupt Sources
Figure 29.3 shows a diagram of the PCA1 interrupt tree. There are five independent event flags that can
be used to generate a PCA1 interrupt. They are as follows: the main PCA1 counter overflow flag (CF1),
which is set upon a 16-bit overflow of the PCA1 counter, an intermediate overflow flag (COVF1), which can
be set on an overflow from the 8th, 9th, 10th, or 11th bit of the PCA1 counter, and the individual flags for
each PCA1 channel (CCF6, CCF7, CCF8, CCF9, CCF10 and CCF11), which are set according to the
operation mode of that module. These event flags are always set when the trigger condition occurs. Each
of these flags can be individually selected to generate a PCA1 interrupt, using the corresponding interrupt
enable flag (ECF1 for CF1, ECOV1 for COVF1, and ECCF1n for each CCFn). PCA1 interrupts must be
globally enabled before any individual interrupt sources are recognized by the processor. PCA1 interrupts
are globally enabled by setting the EA bit and the EPCA1 bit to logic 1.
PCA1 Counter/Timer 16-
PCA1 Counter/Timer 8,
9, 10 or 11-bit Overflow
bit Overflow
PCA Module 10
PCA Module 11
PCA Module 6
PCA Module 7
PCA Module 8
PCA Module 9
W
M
P
1
6
1
n
(for n = 0 to 2)
PCA1CPMn
E
C
O
M
1
n
(CCF10)
(CCF11)
(CCF6)
(CCF7)
(CCF8)
(CCF9)
C
A
P
P
1
n
C
A
P
N
1
n
M
A
T
n
1
O
G
T
1
n
W
M
P
1
n
C
C
E
F
1
n
C
F
1
C
R
1
PCA1CN
Figure 29.3. PCA1 Interrupt Block Diagram
C
C
F
1
1
C
C
F
1
0
C
C
F
9
C
C
F
8
C
C
F
7
C
C
F
6
ECCF10
ECCF11
ECCF6
ECCF7
ECCF8
ECCF9
C
D
L
1
I
PCA1MD
C
P
S
1
2
C
P
S
1
1
0
1
0
1
0
1
0
1
0
1
0
1
C
P
S
1
0
E
C
F
1
Rev. 1.2
0
1
A
R
S
E
L
1
C
O
V
PCA1PWM
F
1
O
E
C
V
1
0
1
C
L
S
E
L
1
1
C
L
S
E
L
1
0
Set 8, 9, 10, or 11 bit Operation
C8051F58x/F59x
EPCA1
0
1
EA
0
1
Interrupt
Priority
Decoder
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