STM8S103F3M6TR STMicroelectronics, STM8S103F3M6TR Datasheet - Page 81
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STM8S103F3M6TR
Manufacturer Part Number
STM8S103F3M6TR
Description
8-bit Microcontrollers - MCU Access line 8-bit MCU 8Kb
Manufacturer
STMicroelectronics
Datasheet
1.STM8S103F3M6TR.pdf
(117 pages)
Specifications of STM8S103F3M6TR
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STM8S103K3 STM8S103F3 STM8S103F2
Electrical characteristics
Figure 36: Typical NRST pull-up resistance vs V
@ 4 temperatures
DD
Figure 37: Typical NRST pull-up current vs V
@ 4 temperatures
DD
The reset network shown in the following figure protects the device against parasitic resets.
The user must ensure that the level on the NRST pin can go below V
max. (see
Table
IL(NRST)
38: I/O static characteristics
), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry,
attention must be taken to the charge/discharge time of the external capacitor to fulfill the
external devices reset timing conditions. Minimum recommended capacity is 100 nF.
DocID15441 Rev 9
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