C8051F509-IMR Silicon Labs, C8051F509-IMR Datasheet - Page 177
C8051F509-IMR
Manufacturer Part Number
C8051F509-IMR
Description
8-bit Microcontrollers - MCU 50 MIPS 64 kB 4 kB SPI UART I2C
Manufacturer
Silicon Labs
Datasheet
1.C8051F510-IMR.pdf
(312 pages)
Specifications of C8051F509-IMR
Rohs
yes
Core
8051
Data Bus Width
8 bit
Processor Series
C8051
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20. Port Input/Output
Digital and analog resources are available through 40 (C8051F500/1/4/5), 33 (C8051F508/9-F510/1) or 25
(C8051F502/3/6/7) I/O pins. Port pins P0.0-P4.7 on the C8051F500/1/4/5, port pins P0.0-P4.0 on
theC8051F508/9-F510/1, and port pins P0.0-P3.0 on the C8051F502/3/6/7 can be defined as general-pur-
pose I/O (GPIO), assigned to one of the internal digital resources, or assigned to an analog function as
shown in Figure 20.3. Port pin P4.0 on the C8051F508/9-F510/1 can be used as GPIO and is shared with
the C2 Interface Data signal (C2D). Similarly, port pin P3.0 is shared with C2D on the C8051F502/3/6/7.
The designer has complete control over which functions are assigned, limited only by the number of phys-
ical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar
Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regard-
less of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 20.3 and Figure 20.4). The registers XBR0, XBR1, XBR2 are defined in SFR Definition 20.1 and
SFR Definition 20.2 and are used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Table 5.3 on page 45.
Highest
Lowest
Priority
Priority
Latches
Port
/SYSCLK
SMBus0
UART0
T0, T1,
/INT0,
CAN0
PCA0
/INT1
SPI0
LIN0
CP0
CP1
P0
P1
P2
P3
P4
(Px.0-Px.7)
8 x 5
8 x 5
Figure 20.1. Port I/O Functional Block Diagram
2
2
4
2
2
2
7
4
2
XBR2, PnSKIP
XBR0, XBR1,
Crossbar
Decoder
Priority
Rev. 1.2
Digital
8
8
8
8
8
PnDMIN Registers
PnMDOUT,
C8051F50x/F51x
Cells
Cells
Cells
Cells
Cells
I/O
I/O
I/O
I/O
I/O
P0
P1
P2
P3
P4
PnMATCH
Registers
PnMASK
External
Pins
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
P4.0
P4.7
Highest
Priority
Lowest
Priority
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