NAND128W3A2BN6E NUMONYX, NAND128W3A2BN6E Datasheet - Page 27

• Manufacturer Part Number: NAND128W3A2BN6E
• Description: IC FLASH 128MBIT 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND128W3A2BN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 128M (16M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Access Time: 12µs
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Voltage, Vcc: 3.3V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 497-5037; 497-5037

NAND128-A, NAND256-A
6.3
Page program
The page program operation is the standard operation to program data to the memory array.
The main area of the memory array is programmed by page, however partial page
programming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be
programmed.
The maximum number of consecutive partial page program operations allowed in the same
page is three. After exceeding this a Block Erase command must be issued before any
further program operations can take place in that page.
Before starting a page program operation a pointer operation can be performed to point to
the area to be programmed. Refer to
operations for programming
Each page program operation consists of the following five steps (see
program
1.
2.
3.
4.
5.
Once the program operation has started the status register can be read using the Read
Status Register command. During program operations the status register only flags errors
for bits set to '1' that have not been successfully programmed to '0'.
During the program operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Once the program operation has completed the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
The device remains in read status register mode until another valid command is written to
the command interface.
Figure 14. Page program operation
1. Before starting a page program operation a pointer operation can be performed. Refer to
Pointer operations
One bus cycle is required to setup the Page Program command
Four bus cycles are then required to input the program address (refer to
Address insertion, x8
The data is then input (up to 528 bytes/ 264 words) and loaded into the page buffer
One bus cycle is required to issue the confirm command to start the P/E/R controller.
The P/E/R controller then programs the data into the array.
RB
I/O
operation):
Page Program
Setup Code
80h
for details.
Address Inputs
devices)
for details.
Section 6.1: Pointer operations
Data Input
(Program Busy time)
Confirm
Code
10h
tBLBH2
Busy
and
Figure 14: Page
Read Status Register
Device operations
Figure 9: Pointer
70h
Section 6.1:
Table 6:
SR0
ai07566
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