S9S08SG8E2VTJR Freescale Semiconductor, S9S08SG8E2VTJR Datasheet - Page 138

• Manufacturer Part Number: S9S08SG8E2VTJR
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTJR

• Rohs: yes
• Core: HCS08
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• On-chip Adc: Yes
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
9.3.3
In 10-bit operation, ADCRH contains the upper two bits of 10-bit conversion data. In 10-bit mode,
ADCRH is updated each time a conversion completes except when automatic compare is enabled and the
compare condition is not met. When configured for 8-bit mode, ADR[9:8] are cleared.
When automatic compare is not enabled, the value stored in ADCRH are the upper bits of the conversion
result. When automatic compare is enabled, the conversion result is manipulated as described in
Section 9.4.5, “Automatic Compare Function”
In 10-bit mode, reading ADCRH prevents the ADC from transferring subsequent conversion data into the
result registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed,
the intermediate conversion data is lost. In 8-bit mode, there is no interlocking with ADCRL. If the MODE
bits are changed, any data in ADCRH becomes invalid.
9.3.4
ADCRL contains the lower eight bits of a 10-bit conversion data, and all eight bits of 8-bit conversion data.
ADCRL is updated each time a conversion completes except when automatic compare is enabled and the
compare condition is not met.
When automatic compare is not enabled, the value stored in ADCRL is the lower eight bits of the
conversion result. When automatic compare is enabled, the conversion result is manipulated as described
in
In 10-bit mode, reading ADCRH prevents the ADC from transferring subsequent conversion data into the
result registers until ADCRL is read. If ADCRL is not read until the after next conversion is completed,
132
Section 9.4.5, “Automatic Compare Function”
ACFGT
ACFE
Field
5
4
Reset:
W
R
Data Result High Register (ADCRH)
Data Result Low Register (ADCRL)
Compare Function Enable — Enables the compare function.
0 Compare function disabled
1 Compare function enabled
Compare Function Greater Than Enable — Configures the compare function to trigger when the result of the
conversion of the input being monitored is greater than or equal to the compare level. The compare function
defaults to triggering when the result of the compare of the input being monitored is less than the compare level.
0 Compare triggers when input is less than compare level
1 Compare triggers when input is greater than or equal to compare level
7
0
0
Table 9-5. ADCSC2 Register Field Descriptions (continued)
= Unimplemented or Reserved
Figure 9-5. Data Result High Register (ADCRH)
0
0
6
MC9S08SG32 Data Sheet, Rev. 8
0
0
5
prior to storage in ADCRH:ADCRL registers.
prior to storage in ADCRH:ADCRL registers.
0
0
4
Description
0
0
3
0
0
2
ADR9
Freescale Semiconductor
0
1
ADR8
0
0