S9S08SG8E2VTJR Freescale Semiconductor, S9S08SG8E2VTJR Datasheet - Page 89

• Manufacturer Part Number: S9S08SG8E2VTJR
• Description: 8-bit Microcontrollers - MCU 9S08 UC W/ 8K 0.25UM SGF
• Manufacturer: Freescale Semiconductor

Specifications of S9S08SG8E2VTJR

• Rohs: yes
• Core: HCS08
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 512 B
• On-chip Adc: Yes
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Interface Type: I2C, SCI, SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

6.6.1
Port A is controlled by the registers listed below.
6.6.1.1
6.6.1.2
Freescale Semiconductor
PTADD[7:6,
PTAD[7:6,
Reserved
Reserved
Reset:
Reset:
7:6, 3:0
7:6, 3:0
Field
Field
3:0]
3:0]
5:4
5:4
W
W
R
R
PTADD7
PTAD7
Port A Registers
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Port A Data Register (PTAD)
0
Port A Data Direction Register (PTADD)
0
7
7
PTADD6
PTAD6
0
0
6
6
Figure 6-4. Port A Data Direction Register (PTADD)
Table 6-3. PTADD Register Field Descriptions
Table 6-2. PTAD Register Field Descriptions
Figure 6-3. Port A Data Register (PTAD)
R
R
0
0
5
5
MC9S08SG32 Data Sheet, Rev. 8
R
R
0
0
4
4
Description
Description
PTADD3
PTAD3
3
0
3
0
PTADD2
PTAD2
Chapter 6 Parallel Input/Output Control
0
0
2
2
PTADD1
PTAD1
0
0
1
1
PTADD0
PTAD0
0
0
0
0
83