CY7C1325G-133AXC Cypress Semiconductor Corp, CY7C1325G-133AXC Datasheet - Page 14

• Manufacturer Part Number: CY7C1325G-133AXC
• Description: IC SRAM 4.5MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1325G-133AXC

• Memory Size: 4.5M (256K x 18)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 6.5 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 225 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Timing Diagrams
Notes
Document Number: 38-05518 Rev. *H
18. On this diagram, when CE is LOW: CE
19. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Data Out (Q)
Data in (D)
ADDRESS
BWE,
BW
ADSP
ADSC
[ A:B]
GW
ADV
CE
CLK
OE
BURST READ
High-Z
(continued)
t ADS
t CES
t AS
A1
t ADH
t CEH
t
t AH
t
CH
OEHZ
Byte write signals are ignored for first cycle when
ADSP initiates burst
t CYC
1
t ADS
t
is LOW, CE
CL
Single WRITE
t
DS
D(A1)
t ADH
t
DH
2
is HIGH and CE
A2
Figure 5. Write Cycle Timing
D(A2)
3
DON’T CARE
is LOW. When CE is HIGH: CE
D(A2 + 1)
t
WES
BURST WRITE
t
WEH
D(A2 + 1)
UNDEFINED
[A:B]
ADV suspends burst
LOW.
[18, 19]
D(A2 + 2)
ADSC extends burst
1
is HIGH or CE
D(A2 + 3)
t ADS
2
is LOW or CE
A3
D(A3)
t ADH
t ADVS
Extended BURST WRITE
t WES
D(A3 + 1)
t ADVH
t WEH
3
is HIGH.
CY7C1325G
D(A3 + 2)
Page 14 of 21
[+] Feedback