CY7C1325G-133AXC Cypress Semiconductor Corp, CY7C1325G-133AXC Datasheet - Page 5

• Manufacturer Part Number: CY7C1325G-133AXC
• Description: IC SRAM 4.5MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1325G-133AXC

• Memory Size: 4.5M (256K x 18)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 6.5 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 225 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Pin Definitions
Document Number: 38-05518 Rev. *H
ADV
ADSP
ADSC
ZZ
DQs
DQP
V
V
V
MODE
NC
NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
DD
SS
DDQ
Name
A,
DQP
B
asynchronous
Power supply Power supply inputs to the core of the device.
synchronous
synchronous
synchronous
synchronous
I/O power
Ground
supply
Input-
Input-
Input-
Input-
Input-
static
I/O-
I/O
(continued)
–
Advance input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved.During normal operation, this pin has to be low or
left floating. ZZ pin has an internal pull-down.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP
Ground for the core of the device.
Power supply for the I/O circuitry.
Selects burst order. When tied to GND selects linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode pin has an internal pull-up.
No connects. Not Internally connected to the die.
No connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins that are not internally connected to
the die.
[A:B]
are placed in a tristate condition.
1
is deasserted HIGH.
Description
CY7C1325G
DD
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