CY7C1325G-133AXC Cypress Semiconductor Corp, CY7C1325G-133AXC Datasheet - Page 6

• Manufacturer Part Number: CY7C1325G-133AXC
• Description: IC SRAM 4.5MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1325G-133AXC

• Memory Size: 4.5M (256K x 18)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 6.5 ns
• Maximum Clock Frequency: 133 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 225 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t
The CY7C1325G supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear burst
sequence. The burst order is user-selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the processor address strobe (ADSP) or the controller
address strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW
enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Three synchronous chip selects (CE
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter/control
logic and presented to the memory core. If the OE input is
asserted LOW, the requested data is available at the data
outputs, a maximum to t
CE
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BW
inputs are asserted active (see Write Cycle Descriptions table for
appropriate states that indicate a write) on the next clock rise, the
Document Number: 38-05518 Rev. *H
1
is HIGH.
[A:B]
CDV
) are ignored during this first clock cycle. If the write
) is 6.5 ns (133 MHz device).
CDV
1
after clock rise. ADSP is ignored if
, CE
1
, CE
2
, CE
[A:B]
2
, and CE
) inputs. A global write
3
1
, CE
are all asserted active,
2
3
, CE
are all asserted
3
) and an
1
is
appropriate data is latched and written into the device. Byte
writes are allowed. During byte writes, BW
BW
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tristated prior to the
presentation of data to DQ
lines are tristated after a write cycle is detected, regardless of the
state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQ
specified address location. Byte writes are allowed. During byte
writes, BW
tristated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tristated prior to the presen-
tation of data to DQ
tristated after a write cycle is detected, regardless of the state of
OE.
Burst Sequences
The CY7C1325G provides an on-chip two bit wraparound burst
counter inside the SRAM. The burst counter is fed by A
can follow either a linear or interleaved burst order. The burst
order is determined by the state of the MODE input. A LOW on
MODE selects a linear burst sequence. A HIGH on MODE
selects an interleaved burst order. Leaving MODE unconnected
causes the device to default to a interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CEs,
ADSP, and ADSC must remain inactive for the duration of t
after the ZZ input returns LOW.
B
controls DQ
A
controls DQ
B
. All I/Os are tristated during a byte write.Since
s
. As a safety precaution, the data lines are
A
, BW
s
. As a safety precaution, the data
1
, CE
B
2
controls DQ
, and CE
[A:D]
CY7C1325G
A
is written into the
controls DQ
3
are all asserted
B
. All I/Os are
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[1:0]
ZZREC
A
, and
[A:B]
and
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)