W9412G6JH-5 Winbond Electronics, W9412G6JH-5 Datasheet
W9412G6JH-5
Specifications of W9412G6JH-5
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W9412G6JH-5 Summary of contents
Page 1
... Precharge ..................................................................................................................... 13 7.6 Burst Termination.......................................................................................................... 13 7.7 Refresh Operation......................................................................................................... 13 7.8 Power Down Mode ....................................................................................................... 14 7.9 Input Clock Frequency Change during Precharge Power Down Mode........................ 14 7.10 Mode Register Operation.............................................................................................. 14 2M × 4 BANKS × 16 BITS DDR SDRAM - 1 - W9412G6JH Publication Release Date: Apr. 02, 2010 Revision A01 ...
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... TIMING WAVEFORMS ............................................................................................................. 34 11.1 Command Input Timing ................................................................................................ 34 11.2 Timing of the CLK Signals ............................................................................................ 34 11.3 Read Timing (Burst Length = 4) ................................................................................... 35 11.4 Write Timing (Burst Length = 4).................................................................................... 36 11.5 DM, DATA MASK (W9412G6JH) ................................................................................. 37 11.6 Mode Register Set (MRS) Timing................................................................................. 38 W9412G6JH Publication Release Date: Apr. 02, 2010 - 2 - Revision A01 ...
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... Precharged/Active Power Down Mode Entry and Exit Timing .................................... 49 11.25 Input Clock Frequency Change during Precharge Power Down Mode Timing .......... 49 11.26 Self Refresh Entry and Exit Timing ............................................................................. 50 12. Package Specification............................................................................................................... 51 12.1 66L TSOP – 400 mil ..................................................................................................... 51 13. REVISION HISTORY ................................................................................................................ 52 W9412G6JH Publication Release Date: Apr. 02, 2010 - 3 - Revision A01 ...
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... GENERAL DESCRIPTION W9412G6JH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM); organized as 2M words × 4 banks × 16 bits. W9412G6JH delivers a data bandwidth 500M words per second (-4). To fully comply with the personal computer industrial standard, W9412G6JH is sorted into two speed grades: -4 and -5. The -4 is compliant to the DDR500/CL3 and CL4 specification ...
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... Operating Current: One Bank Active-Precharge DD0 I Operating Current: One Bank Active-Read-Precharge DD1 I Burst Operation Current DD4R I Burst Operation Current DD4W I Auto Refresh Burst current DD5 I Self-Refresh Current DD6 DESCRIPTION 2 W9412G6JH MIN/MAX. -4 Min. - 7.5 nS Max. - Min. - Max. - Min Max Min Max Min Min. ...
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... DQ7 NC V DDQ LDQS LDM WE CAS RAS CS NC BA0 BA1 A10/ Publication Release Date: Apr. 02, 2010 - 6 - W9412G6JH DQ15 64 V SSQ 63 DQ14 62 DQ13 61 V DDQ 60 DQ12 59 DQ11 58 V SSQ 57 DQ10 56 DQ9 55 V DDQ 54 DQ8 SSQ 51 UDQS REF UDM 47 46 CLK 45 CLK CKE ...
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... Ground for logic circuit inside DDR SDRAM. Power for I/O Separated power from V Buffer improve noise. Ground for I/O Separated ground from V Buffer improve noise. No Connection No connection - 7 - W9412G6JH DESCRIPTION ) define the command CS , used for output buffer used for output buffer Publication Release Date: Apr. 02, 2010 Revision A01 ...
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... CELL ARRAY BANK #0 SENSE AMPLIFIER PREFETCH REGISTER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER NOTE: The cell array configuration is 4096 * 512 * W9412G6JH COLUMN DECODER CELL ARRAY BANK #1 SENSE AMPLIFIER DQ BUFFER DQ15 COLUMN DECODER CELL ARRAY BANK #3 SENSE AMPLIFIER Publication Release Date: Apr ...
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... DDQ and V TT MRS PREA AREF 2 Clock min 200 Clock min. DLL reset with A8 = High Initialization sequence after power- W9412G6JH . REF AREF MRS t RFC 2 Clock min. t RFC Disable DLL reset with A8 = Low Publication Release Date: Apr. 02, 2010 Revision A01 ANY CMD ...
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... Read with Auto-precharge Command ( RAS = “H”, CAS = ”L” ”H”, BA0, BA1 = Bank, A10 = ”H” Column Address) The Read with Auto-precharge command automatically performs the Precharge operation after the Read operation. W9412G6JH Publication Release Date: Apr. 02, 2010 - 10 - Revision A01 ...
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... The refresh addressing is generated by the internal refresh controller. This makes the address bits ”Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO CK - (BL/ Publication Release Date: Apr. 02, 2010 - 11 - W9412G6JH Revision A01 ...
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... Refer to the diagrams for Read operation. (maximum). REFI because time is required for the completion of any internal refresh in from the Bank Activate command, the data is read out sequentially W9412G6JH . REFI Publication Release Date: Apr. 02, 2010 Revision A01 ...
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... In Self Refresh mode, all input/output buffers are disabled, from the bank activate command. The input data is latched RCD from the bank activate command. RAS(max) . RFC Publication Release Date: Apr. 02, 2010 - 13 - W9412G6JH . Therefore, each RAS (max) Revision A01 ...
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... Burst Length field (A2 to A0) This field specifies the data length for column access using the pins and sets the Burst Length and 8 words BURST LENGTH 0 Reserved 1 2 words 0 4 words 1 8 words x Reserved Publication Release Date: Apr. 02, 2010 - 14 - W9412G6JH Revision A01 ...
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... A0) not carried from words (address bit A0, A1) Not carried from words (address bits A2, A1 and A0) Not carried from Addressing Sequence of Interleave Mode ACCESS ADDRESS - 15 - W9412G6JH BURST LENGTH BURST LENGTH 2 words 4 words 8 words Publication Release Date: Apr. 02, 2010 Revision A01 ...
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... These bits are reserved for future operations. They must be set to “0” for normal operation. A4 CAS LATENCY A11-A0 Regular MRS Cycle Extended MRS Cycle Reserved DLL Enable Disable BUFFER STRENGTH 100% Strength 60% Strength Reserved 30% Strength Publication Release Date: Apr. 02, 2010 - 16 - W9412G6JH Reserved Reserved Reserved 2.5 Reserved Revision A01 ...
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... CKEn signal is input level when commands are issued. CKEn-1 signal is input level one clock cycle before the commands are issued. 3. These are state designated by the BA0, BA1 signals. 4. LDM, UDM (W9412G6JH). 5. Power Down Mode can not entry in the burst cycle. BA0, ...
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... BST BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA BA, RA ACT L BA, A10 PRE/PREA X AREF/SELF L Op-Code MRS/EMRS - 18 - W9412G6JH ACTION NOP NOP ILLEGAL ILLEGAL Row activating NOP Refresh or Self refresh Mode register accessing NOP NOP Begin read: Determine AP Begin write: Determine AP ILLEGAL Precharge ILLEGAL ...
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... BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS - 19 - W9412G6JH ACTION NOTES Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ...
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... X READ/WRIT X ACT/PRE/PREA X AREF/SELF/MRS/EMRS X DSL X NOP L X BST X READ/WRIT ACT/PRE/PREA/ARE X F/SELF/MRS/EMRS W9412G6JH ACTION NOTES NOP -> Row active after t WR NOP -> Row active after t WR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP -> Enter precharge after t WR NOP -> Enter precharge after t WR ILLEGAL ...
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... X X Enter Power down Self Refresh ILLEGAL ILLEGAL Power down Refer to Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power down Refer to Function Truth Table - 21 - W9412G6JH ACTION NOTES XSNR XSNR IS Publication Release Date: Apr. 02, 2010 Revision A01 ...
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... PDEX ACT PDEX PD ROW ACTIVE Write Read Read A Write A Read A PRE PRE PRE PRE CHARGE PRE - 22 - W9412G6JH SELF REFRESH SREFX AUTO REFRESH PD POWER DOWN BST Read Read Read Read A Read A Automatic Sequence Command Sequence Publication Release Date: Apr. 02, 2010 Revision A01 ...
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... TYP. 2.3 2.4 2.3 -4 2 DDQ V - 0.04 V REF V + 0.15 REF -0.3 -0.3 0. 0.31 REF - 0 0.2 DDQ 0.2 DDQ +1.5V with a pulse width < W9412G6JH RATING UNIT -0 0.5 V DDQ - °C -55 ~ 150 °C 260 ° MAX. UNIT NOTES 2.5 2 2.7 V 2 ...
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... OUT (DC) DDQ OUT MIN. 2.0 3.0 1 Pin 0V < V < 1.35V DD REF IN < OUT DDQ , min. V REF TT , max REF TT , min. V REF min. V REF TT , max REF W9412G6JH DELTA MAX. (MAX.) 4.0 0.5 5.0 0.25 5.5 0.5 1.5 - UNIT MIN. MAX µ µA V +0. -0. - ...
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... CK CK OUT min; Vin = V for DQ, DQS and DM REF min min max for DQ, DQS and DM IL min; min; One Bank Active-Precharge; IH min; = 0mA = t min RFC external clock on 0mA W9412G6JH MAX. UNIT NOTES - 140 120 135 115 75 70 min 2 2 170 150 Publication Release Date: Apr. 02, 2010 ...
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... -0.5 HP 0.9 1.1 0.4 0.6 0.4 0.4 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.6 0.85 1.15 0.6 0.6 0.7 0.7 2.2 0.7 -0.7 0.7 0.5 1 200 15.6 8 Publication Release Date: Apr. 02, 2010 - 26 - W9412G6JH -5 UNIT NOTES MIN. MAX 100000 7 -0.7 0 ...
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... V = 1.11V. DDQ system supply for signal termination resistors is expected to be set TT . REF and V .Transition (rise and fall) of input signals have a fixed IH min(AC) IL max(AC) contains more than one decimal place, the result is rounded W9412G6JH VALUE 0.31 IH REF 0.31 IL REF V 0 REF ...
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... These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. (23) Slew Rate is measured between ICK ICK V V ISO(min) ISO(max) (ac) and V (ac Publication Release Date: Apr. 02, 2010 - 28 - W9412G6JH ICK ID(AC) Revision A01 ...
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... TYPICAL MINIMUM RANGE (V/NS) (V/NS) 1.2 ~ 2.5 0.7 1.2 ~ 2.5 0 W9412G6JH DDR400 UNIT NOTES MAX. MIN. MAX. 4.0 0.5 4.0 V/ UNIT NOTES UNIT NOTES UNIT NOTES ...
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... Max. amplitude = 1. 0.5 0.68751.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.06.3125 6.5 7.0 Figure 3: Address and Control AC Overshoot and Undershoot Definition DDR500 MIN. 0.67 Overshoot Time (nS W9412G6JH DDR400 NOTES MAX. MIN. MAX. 1.5 0.67 1 SPECIFICATION DDR500 DDR400 1 ...
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... Max. amplitude = 1. 0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0 Figure 4: DQ/DM/DQS AC Overshoot and Undershoot Definition Overshoot Time (nS W9412G6JH SPECIFICATION DDR500 DDR400 1.2 V 1.2 V 1.2 V 1.2 V 1.44 V-nS 1.44 V-nS 1.44 V-nS 1.44 V-nS Max ...
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... C (T Ambient Minimum Ambient Maximum Ambient), V Test point 50 Ω VSSQ VDDQ 50 Ω Test point /2 - 320 mV ± 250 mV) DDQ /2 + 320 mV ± 250 mV) DDQ = nominal, typical process DDQ = minimum, slow-slow process DDQ = maximum, fast-fast process DDQ Publication Release Date: Apr. 02, 2010 - 32 - W9412G6JH Revision A01 ...
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... DQ, DM, and DQS slew similarly for rising transitions. IL(AC) IH(DC) IL(DC) and t in the case where the I/O slew rate is below 0.5 V/nS. The W9412G6JH and t of 100 IH(AC) IL(AC) Publication Release Date: Apr. 02, 2010 Revision A01 IH(DC) ...
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... TIMING WAVEFORMS 11.1 Command Input Timing CLK CLK CS RAS CAS WE A0~A11 BA0,1 11.2 Timing of the CLK Signals Refer to the Command Truth Table Publication Release Date: Apr. 02, 2010 - 34 - W9412G6JH Revision A01 ...
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... CLK CMD READ ADD Col CAS Latency = 2 Hi-Z DQS Hi-Z Output (Data) CAS Latency = 3 Hi-Z DQS Hi-Z Output (Data) Notes : The correspondence of LDQS, UDQS to DQ. (W9412G6JH) LDQS DQ0~7 UDQS DQ8~ DQSCK t DQSCK t RPRE t QH Preamble DQSQ QH DQSQ QA0 DA0 DA1 QA1 ...
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... DQSH Postamble DA0 DA1 DA1 DA2 DA3 DSS DSH DSS DSH WPST DQSH DQSL DQSH Postamble DA0 DA1 DA2 DA3 DSH DSS DSH DSS DQSH DQSL DQSH WPST Postamble DA0 DA1 DA2 DA3 W9412G6JH Publication Release Date: Apr. 02, 2010 Revision A01 ...
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... DM, DATA MASK (W9412G6JH) W9412G6JH Publication Release Date: Apr. 02, 2010 - 37 - Revision A01 ...
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... Addressing Mode CAS Latency A6 A7 Reserved "0" A8 DLL Reset "0" A9 A10 "0" Reserved A11 "0" Mode Register Set BA0 "0" or Extended Mode Register Set "0" BA1 * "Reserved" should stay "0" during MRS cycle. W9412G6JH t MRD NEXT CMD Burst Length Sequential Reserved ...
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... A8 "0" Reserved A9 "0" A10 "0" A11 "0" BA0 Mode Register Set "0" or Extended Mode BA1 "0" Register Set * "Reserved" should stay "0" during EMRS cycle. W9412G6JH t MRD NEXT CMD DLL Switch A0 Enable 0 Disable Buffer Strength 100% Strength 0 0 60% Strength 0 1 Reserved ...
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... Notes: CL=2 shown; same command operation timing with CL = 2,5 and CL=3 In this case, the internal precharge operation begin after BL/2 cycle from READA command. AP Represents the start of internal precharging. The Read with Auto-precharge command cannot be interrupted by any other command RAS READA READA READA W9412G6JH t RP ACT ACT ACT ...
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... Represents the start of internal precharging. The Read with Auto-precharge command cannot be interrupted by any other command. – (BL/2) × t RAS (min RAS READA Q0 Q1 READA READA W9412G6JH t RP ACT AP AP ACT Q3 AP ACT (min) has command. RAS Publication Release Date: Apr. 02, 2010 Revision A01 ...
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... WRITA CMD DQS BL=4 WRITA CMD DQS BL=8 WRITA CMD DQS The Write with Auto-precharge command cannot be interrupted by any other command. AP Represents the start of internal precharging. t DAL AP t DAL W9412G6JH ACT ACT t DAL AP ACT Publication Release Date: Apr. 02, 2010 Revision A01 ...
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... Read Interrupted by Read ( 11.12 Burst Read Stop ( W9412G6JH Publication Release Date: Apr. 02, 2010 - 43 - Revision A01 ...
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... Read Interrupted by Write & BST ( Burst Read cycle must be terminated by BST Command to avoid I/O conflict. 11.14 Read Interrupted by Precharge ( CLK CLK CMD READ CAS Latency = 2 DQS DQ CAS Latency = 3 DQS DQ PRE CAS Latency CAS Latency W9412G6JH Publication Release Date: Apr. 02, 2010 Revision A01 ...
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... Write Interrupted by Write ( 11.16 Write Interrupted by Read ( CLK CLK CMD WRIT DQS Data must be masked by DM READ t WTR Data masked by READ command, DQS input ignored W9412G6JH Publication Release Date: Apr. 02, 2010 Revision A01 ...
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... CLK CMD WRIT DQS 11.18 Write Interrupted by Precharge ( CLK CLK CMD WRIT DQS READ t WTR D2 D3 Data must be masked by DM PRE Data must be Data masked by PRE masked by DM command, DQS input ignored W9412G6JH ACT Publication Release Date: Apr. 02, 2010 Revision A01 ...
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... RAS(a) t RCD(b) t RAS(b) Preamble CL(a) APa tRC(b) tRC(a) ACTb READAa READAb tRAS(a) tRCD(b) tRAS(b) Preamble CL(a) Q0a Q1a APa - 47 - W9412G6JH t RRD READAb ACTa ACTb t RP(a) t RP(b) Postamble Preamble Postamble CL(b) Q0a Q1a Q0b Q1b APb tRRD ACTa ACTb tRP(a) tRP(b) Postamble ...
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... READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d APa/b/c/d : Auto Pre. of bank a/b/c/d 11.22 4 Bank Interleave Read Operation ( RC( RRD RRD ACTb ACTc READAa ACTd tRCD(a) t RAS(a) t RCD(b) t RAS(b) CL( W9412G6JH t RRD READAb ACTa READAc RCD(c) t RAS(c) t RCD(d) t RAS(d) Preamble Postamble Preamble CL(b) Q0a Q1a Q0b Q1b APb APa Publication Release Date: Apr ...
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... CLK CLK CMD NOP NOP CKE t RP Minmum 2 clocks required before changing frequency NOP t IS Frequency Change Occurs here Stable new clock before power down exit Publication Release Date: Apr. 02, 2010 - 49 - W9412G6JH DLL NOP NOP CMD RESET 200 clocks Revision A01 ...
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... NOP SELF t RP Entry SELF Entry Note: If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit SELEX Exit t XSNR t XSRD SELFX NOP ACT NOP Exit Publication Release Date: Apr. 02, 2010 - 50 - W9412G6JH NOP CMD READ NOP Revision A01 ...
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... PACKAGE SPECIFICATION 12.1 66L TSOP – 400 mil Publication Release Date: Apr. 02, 2010 - 51 - W9412G6JH Revision A01 ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. PAGE All Initial formally data sheet Important Notice - 52 - W9412G6JH DESCRIPTION Publication Release Date: Apr. 02, 2010 Revision A01 ...